diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst
index e9be51fda..728adb1e0 100644
--- a/docs/source/manual/fpga_verilog/testbench.rst
+++ b/docs/source/manual/fpga_verilog/testbench.rst
@@ -1,3 +1,5 @@
+.. _fpga_verilog_testbench:
+
 Testbench
 ---------
 
diff --git a/docs/source/tutorials/compile.rst b/docs/source/tutorials/compile.rst
index e7db5a059..5183be503 100644
--- a/docs/source/tutorials/compile.rst
+++ b/docs/source/tutorials/compile.rst
@@ -8,7 +8,7 @@ General Guidelines
 OpenFPGA uses CMake to generate the Makefile scripts
 In general, please follow the steps to compile
 
-::
+.. code-block:: shell
 
   git clone https://github.com/LNIS-Projects/OpenFPGA.git
   cd OpenFPGA
@@ -27,7 +27,7 @@ In general, please follow the steps to compile
 
 To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository
 
-::
+.. code-block:: shell
 
   python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs
 
@@ -49,7 +49,7 @@ Docker
 If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed).
 For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command
 
-::
+.. code-block:: shell
 
   docker run lnis/open_fpga:release
 
@@ -57,7 +57,7 @@ For the ease of the customer first experience, a Dockerfile is provided in the O
 
 Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands
 
-::
+.. code-block:: shell
 
   docker build . -t open_fpga
   docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst
index 610b09b35..e854a08c6 100644
--- a/docs/source/tutorials/design_flow/index.rst
+++ b/docs/source/tutorials/design_flow/index.rst
@@ -7,4 +7,6 @@ Design Flows
 .. toctree::
    :maxdepth: 2
 
+   blif_to_verification
+
    verilog_to_gds2