diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp index 772ee8f57..24c0e8c7d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp @@ -75,12 +75,6 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, arch.sram_inf.verilog_sram_inf_orgz->spice_model); config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, sram_model); - /* Create a vector of segments. TODO: should come from DeviceContext */ - std::vector L_segment_vec; - for (int i = 0; i < arch.num_segments; ++i) { - L_segment_vec.push_back(arch.Segments[i]); - } - /* Add constant generator modules: VDD and GND */ build_constant_generator_modules(module_manager); @@ -88,7 +82,7 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, * This should be done prior to other steps in this function, * because they will be instanciated by other primitive modules */ - build_user_defined_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); + build_user_defined_modules(module_manager, arch.spice->circuit_lib); /* Build elmentary modules */ build_essential_modules(module_manager, arch.spice->circuit_lib); @@ -103,7 +97,7 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, build_lut_modules(module_manager, arch.spice->circuit_lib); /* Build wire modules */ - build_wire_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); + build_wire_modules(module_manager, arch.spice->circuit_lib); /* Build memory modules */ build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 8ebe2ab0e..1769b9d31 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -155,6 +155,12 @@ void build_essential_modules(ModuleManager& module_manager, "Building essential (inverter/buffer/logic gate) modules..."); for (const auto& circuit_model : circuit_lib.models()) { + /* We only care about user-defined models */ + if ( (false == circuit_lib.model_verilog_netlist(circuit_model).empty()) + && (false == circuit_lib.model_spice_netlist(circuit_model).empty()) ) { + continue; + } + if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { build_invbuf_module(module_manager, circuit_lib, circuit_model); continue; @@ -184,8 +190,7 @@ void build_essential_modules(ModuleManager& module_manager, * to the module_manager ********************************************************************/ void build_user_defined_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& routing_segments) { + const CircuitLibrary& circuit_lib) { /* Start time count */ clock_t t_start = clock(); @@ -196,7 +201,7 @@ void build_user_defined_modules(ModuleManager& module_manager, for (const auto& model : circuit_lib.models()) { /* We only care about user-defined models */ if ( (true == circuit_lib.model_verilog_netlist(model).empty()) - && (true == circuit_lib.model_verilog_netlist(model).empty()) ) { + && (true == circuit_lib.model_spice_netlist(model).empty()) ) { continue; } /* Skip Routing channel wire models because they need a different name. Do it later */ @@ -273,7 +278,7 @@ void rename_primitive_module_port_names(ModuleManager& module_manager, for (const CircuitModelId& model : circuit_lib.models()) { /* We only care about user-defined models */ if ( (true == circuit_lib.model_verilog_netlist(model).empty()) - && (true == circuit_lib.model_verilog_netlist(model).empty()) ) { + && (true == circuit_lib.model_spice_netlist(model).empty()) ) { continue; } /* Skip Routing channel wire models because they need a different name. Do it later */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h index 417f265b6..703d8a285 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h @@ -8,8 +8,7 @@ void build_essential_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib); void build_user_defined_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& routing_segments); + const CircuitLibrary& circuit_lib); void build_constant_generator_modules(ModuleManager& module_manager); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp index 6a064fa37..fd7527b6d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp @@ -52,51 +52,6 @@ void build_wire_module(ModuleManager& module_manager, add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); } -/******************************************************************** - * Build module of a routing track wire segment - * Routing track wire, which is 1-input and dual output - * This type of wires are used in the global routing architecture. - * One of the output is wired to another Switch block multiplexer, - * while the mid-output is wired to a Connection block multiplexer. - * - * | CLB | - * +------------+ - * ^ - * | - * +------------------------------+ - * | Connection block multiplexer | - * +------------------------------+ - * ^ - * | mid-output +-------------- - * +--------------------+ | - * input --->| Routing track wire |--------->| Switch Block - * +--------------------+ output | - * +-------------- - * - *******************************************************************/ -static -void build_routing_wire_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& wire_model, - const std::string& wire_subckt_name) { - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Make sure the port size is what we want */ - VTR_ASSERT (1 == input_ports.size()); - VTR_ASSERT (1 == output_ports.size()); - VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); - VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId wire_module = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model, wire_subckt_name); - - /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_prefix(output_ports[0])), circuit_lib.port_size(output_ports[0])); - module_manager.add_port(wire_module, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); -} - /******************************************************************** * This function will only create wire modules with a number of * ports that are defined by users. @@ -104,8 +59,7 @@ void build_routing_wire_module(ModuleManager& module_manager, * by Verilog/SPICE writers *******************************************************************/ void build_wire_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::vector routing_segments) { + const CircuitLibrary& circuit_lib) { /* Start time count */ clock_t t_start = clock(); @@ -122,23 +76,6 @@ void build_wire_modules(ModuleManager& module_manager, build_wire_module(module_manager, circuit_lib, wire_model); } - for (const auto& seg : routing_segments) { - VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); - VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); - /* Bypass user-defined circuit models */ - if ( (!circuit_lib.model_spice_netlist(seg.circuit_model).empty()) - && (!circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) ) { - continue; - } - /* Give a unique name for subckt of wire_model of segment, - * circuit_model name is unique, and segment id is unique as well - */ - std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); - - /* Print a Verilog module */ - build_routing_wire_module(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); - } - /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h index a68eb22b0..193071526 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h @@ -14,7 +14,6 @@ #include "module_manager.h" void build_wire_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::vector routing_segments); + const CircuitLibrary& circuit_lib); #endif