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further clean-up sample arch.xml

This commit is contained in:
tangxifan 2020-01-17 09:38:35 -07:00
parent 910c69d7e5
commit aa070b2a41
2 changed files with 40 additions and 21 deletions
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32
libopenfpga/libarchopenfpga/arch/sample_arch.xml
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@ -8,20 +8,26 @@
each primitives in FPGA architecture each primitives in FPGA architecture
--> -->
<openfpga_architecture> <openfpga_architecture>
<technology> <technology_library>
<library type="academia" corner="TOP_TT" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/> <transistors name="logic" type="logic">
<transistors name="logic" type="logic" pn_ratio="2" model_ref="M" vdd="0.9"> <model type="academia" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/> <design vdd="0.9" pn_ratio="2"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/> <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</transistors> </transistors>
<transistors name="io" type="io" pn_ratio="3" model_ref="M" vdd="2.5"> <transistors name="io" type="io"/>
<nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/> <model type="academia" corner="TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/> <design vdd="2.5" pn_ratio="3"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</transistors> </transistors>
<rram_devices> <rram name="mem_rram">
<rram model_name="mem_rram" rlrs="1e4" rhrs="1e5" variation="mem_rram_var"> <model type="academia" ref="X" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/rram.pm"/>
<rram model_name="logic_rram" rlrs="5e3" rhrs="20e6" variation="logic_rram_var"> <device rlrs="1e4" rhrs="1e5" variation="mem_rram_var"/>
</rram_devices> </rram>
<rram name="logic_rram">
<model type="academia" ref="X" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/rram.pm"/>
<device rlrs="5e3" rhrs="20e6" variation="logic_rram_var"/>
</rram> </rram>
<device_variation> <device_variation>
<variation name="logic_transistor_var" abs_variation="0.1" num_sigma="3"/> <variation name="logic_transistor_var" abs_variation="0.1" num_sigma="3"/>
@ -29,7 +35,7 @@
<variation name="mem_rram_var" abs_variation="0.1" num_sigma="3"/> <variation name="mem_rram_var" abs_variation="0.1" num_sigma="3"/>
<variation name="logic_rram_var" abs_variation="0.1" num_sigma="3"/> <variation name="logic_rram_var" abs_variation="0.1" num_sigma="3"/>
</device_variation> </device_variation>
</technology> </technology_library>
<circuit_library> <circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true"> <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1"/> <design_technology type="cmos" topology="inverter" size="1"/>

29
libopenfpga/libarchopenfpga/src/technology_library.h
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@ -18,23 +18,36 @@
*******************************************************************/ *******************************************************************/
enum e_tech_lib_type { enum e_tech_lib_type {
TECH_LIB_INDUSTRY, TECH_LIB_INDUSTRY,
TECH_LIB_ACADEMIA TECH_LIB_ACADEMIA,
NUM_TECH_LIB_TYPES
}; };
/* Strings correspond to each technology library type */
constexpr std::array<const char*, NUM_TECH_LIB_TYPES> TECH_LIB_TYPE_STRING = {{"industry", "academia"}};
/******************************************************************** /********************************************************************
* Types of transistors which may be defined in a technology library * Types of transistor groups which may be defined in a technology library
* We categorize the transistors in terms of their usage in FPGA architecture * We categorize the transistors in terms of their usage in FPGA architecture
* 1. NMOS transistor used in datapath logic * 1. NMOS transistor
* 2. PMOS transistor used in datapath logic * 2. PMOS transistor
* 3. NMOS transistor used in the I/O blocks
* 3. PMOS transistor used in the I/O blocks
*******************************************************************/ *******************************************************************/
enum e_tech_lib_trans_type { enum e_tech_lib_trans_type {
TECH_LIB_TRANS_NMOS, TECH_LIB_TRANS_NMOS,
TECH_LIB_TRANS_PMOS, TECH_LIB_TRANS_PMOS,
TECH_LIB_TRANS_IO_NMOS,
TECH_LIB_TRANS_IO_PMOS
}; };
/* Strings correspond to transistor type type */
constexpr std::array<const char*, NUM_TECH_LIB_TYPES> TECH_LIB_TRANS_TYPE_STRING = {{"industry", "academia"}};
/********************************************************************
* Types of transistors which may be defined in a technology library
* 1. NMOS transistor
* 2. PMOS transistor
*******************************************************************/
enum e_tech_lib_trans_type {
TECH_LIB_TRANS_NMOS,
TECH_LIB_TRANS_PMOS,
};
/* Strings correspond to transistor type type */
constexpr std::array<const char*, NUM_TECH_LIB_TYPES> TECH_LIB_TRANS_TYPE_STRING = {{"industry", "academia"}};
/******************************************************************** /********************************************************************
* Process corners supported * Process corners supported