riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

formatting

This commit is contained in:
alaindargelas 2024-03-05 10:16:32 -08:00
parent fcaaba0e55
commit a9f5545efd
1 changed files with 159 additions and 160 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -84,8 +84,8 @@ void print_verilog_testbench_fpga_instance(
module_manager.module_port(top_module, module_port_id);
/* Bypass dummy port: the port does not exist at core module */
if (io_name_map.fpga_top_port_is_dummy(module_port)) {
ModulePortId core_module_port = module_manager.find_module_port(
core_module, module_port.get_name());
ModulePortId core_module_port =
module_manager.find_module_port(core_module, module_port.get_name());
if (!module_manager.valid_module_port_id(core_module,
core_module_port)) {
/* Print the wire for the dummy port */
@ -132,8 +132,7 @@ void print_verilog_testbench_benchmark_instance(
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix,
const std::string& output_port_postfix,
const std::string& input_port_postfix, const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_port_postfix, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
@ -655,8 +654,8 @@ void print_verilog_testbench_check(
print_verilog_comment(
fp, std::string("----- Begin checking output vectors -------"));
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(
clock_port_names, default_clock_name);
std::vector<BasicPort> clock_ports =
generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
print_verilog_comment(fp,
std::string("----- Skip the first falling edge of "
@ -992,8 +991,8 @@ void print_verilog_testbench_shared_input_ports(
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_ports,
const std::string& shared_input_port_postfix, const bool& use_reg_port) {
const bool& include_clock_ports, const std::string& shared_input_port_postfix,
const bool& use_reg_port) {
/* Validate the file stream */
valid_file_stream(fp);