formatting
This commit is contained in:
alaindargelas
parent
fcaaba0e55
commit
a9f5545efd
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@ -35,16 +35,16 @@ namespace openfpga {
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);
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*******************************************************************/
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void print_verilog_testbench_fpga_instance(
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& top_module, const ModuleId& core_module,
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const std::string& top_instance_name, const std::string& net_postfix,
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const IoNameMap& io_name_map, const bool& explicit_port_mapping) {
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& top_module, const ModuleId& core_module,
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const std::string& top_instance_name, const std::string& net_postfix,
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const IoNameMap& io_name_map, const bool& explicit_port_mapping) {
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/* Validate the file stream */
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valid_file_stream(fp);
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/* Include defined top-level module */
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print_verilog_comment(
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fp, std::string("----- FPGA top-level module to be capsulated -----"));
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fp, std::string("----- FPGA top-level module to be capsulated -----"));
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/* Precheck on the top module and decide if we need to consider I/O naming
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* - If we do have a fpga_core module added, and dut is fpga_top, we need a
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@ -68,7 +68,7 @@ void print_verilog_testbench_fpga_instance(
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for (const ModulePortId& module_port_id :
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module_manager.module_ports(top_module)) {
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BasicPort module_port =
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module_manager.module_port(top_module, module_port_id);
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module_manager.module_port(top_module, module_port_id);
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BasicPort net_port = module_port;
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net_port.set_name(module_port.get_name() + net_postfix);
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port2port_name_map[module_port.get_name()] = net_port;
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@ -81,11 +81,11 @@ void print_verilog_testbench_fpga_instance(
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for (const ModulePortId& module_port_id :
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module_manager.module_ports(top_module)) {
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BasicPort module_port =
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module_manager.module_port(top_module, module_port_id);
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module_manager.module_port(top_module, module_port_id);
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/* Bypass dummy port: the port does not exist at core module */
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if (io_name_map.fpga_top_port_is_dummy(module_port)) {
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ModulePortId core_module_port = module_manager.find_module_port(
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core_module, module_port.get_name());
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ModulePortId core_module_port =
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module_manager.find_module_port(core_module, module_port.get_name());
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if (!module_manager.valid_module_port_id(core_module,
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core_module_port)) {
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/* Print the wire for the dummy port */
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@ -128,17 +128,16 @@ std::string escapeNames(const std::string& original) {
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* Instanciate the input benchmark module
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*******************************************************************/
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void print_verilog_testbench_benchmark_instance(
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std::fstream& fp, const std::string& module_name,
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const std::string& instance_name,
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const std::string& module_input_port_postfix,
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const std::string& module_output_port_postfix,
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const std::string& input_port_postfix,
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const std::string& output_port_postfix,
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const std::vector<std::string>& clock_port_names,
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const bool& include_clock_port_postfix, const AtomContext& atom_ctx,
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const VprNetlistAnnotation& netlist_annotation,
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const PinConstraints& pin_constraints, const BusGroup& bus_group,
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const bool& use_explicit_port_map) {
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std::fstream& fp, const std::string& module_name,
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const std::string& instance_name,
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const std::string& module_input_port_postfix,
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const std::string& module_output_port_postfix,
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const std::string& input_port_postfix, const std::string& output_port_postfix,
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const std::vector<std::string>& clock_port_names,
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const bool& include_clock_port_postfix, const AtomContext& atom_ctx,
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const VprNetlistAnnotation& netlist_annotation,
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const PinConstraints& pin_constraints, const BusGroup& bus_group,
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const bool& use_explicit_port_map) {
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/* Validate the file stream */
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valid_file_stream(fp);
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@ -328,15 +327,15 @@ void print_verilog_testbench_benchmark_instance(
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* by default
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*******************************************************************/
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void print_verilog_testbench_connect_fpga_ios(
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& top_module, const AtomContext& atom_ctx,
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const PlacementContext& place_ctx, const IoLocationMap& io_location_map,
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const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group,
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const std::string& net_name_postfix,
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const std::string& io_input_port_name_postfix,
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const std::string& io_output_port_name_postfix,
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const std::vector<std::string>& clock_port_names,
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const size_t& unused_io_value) {
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std::fstream& fp, const ModuleManager& module_manager,
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const ModuleId& top_module, const AtomContext& atom_ctx,
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const PlacementContext& place_ctx, const IoLocationMap& io_location_map,
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const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group,
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const std::string& net_name_postfix,
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const std::string& io_input_port_name_postfix,
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const std::string& io_output_port_name_postfix,
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const std::vector<std::string>& clock_port_names,
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const size_t& unused_io_value) {
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/* Validate the file stream */
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valid_file_stream(fp);
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@ -360,25 +359,25 @@ void print_verilog_testbench_connect_fpga_ios(
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std::map<ModulePortId, std::vector<bool>> io_used;
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for (const ModulePortId& module_io_port_id : module_io_ports) {
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const BasicPort& module_io_port =
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module_manager.module_port(top_module, module_io_port_id);
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module_manager.module_port(top_module, module_io_port_id);
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io_used[module_io_port_id] =
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std::vector<bool>(module_io_port.get_width(), false);
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std::vector<bool>(module_io_port.get_width(), false);
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}
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/* Type mapping between VPR block and Module port */
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std::map<AtomBlockType, ModuleManager::e_module_port_type>
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atom_block_type_to_module_port_type;
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atom_block_type_to_module_port_type;
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atom_block_type_to_module_port_type[AtomBlockType::INPAD] =
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ModuleManager::MODULE_GPIN_PORT;
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ModuleManager::MODULE_GPIN_PORT;
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atom_block_type_to_module_port_type[AtomBlockType::OUTPAD] =
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ModuleManager::MODULE_GPOUT_PORT;
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ModuleManager::MODULE_GPOUT_PORT;
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/* See if this I/O should be wired to a benchmark input/output */
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/* Add signals from blif benchmark and short-wire them to FPGA I/O PADs
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* This brings convenience to checking functionality
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*/
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print_verilog_comment(
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fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----"));
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fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----"));
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for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
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/* Bypass non-I/O atom blocks ! */
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@ -392,17 +391,17 @@ void print_verilog_testbench_connect_fpga_ios(
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* or should find a GPOUT for OUTPAD
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*/
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std::pair<ModulePortId, size_t> mapped_module_io_info =
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std::make_pair(ModulePortId::INVALID(), -1);
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std::make_pair(ModulePortId::INVALID(), -1);
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for (const ModulePortId& module_io_port_id : module_io_ports) {
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const BasicPort& module_io_port =
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module_manager.module_port(top_module, module_io_port_id);
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module_manager.module_port(top_module, module_io_port_id);
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/* Find the index of the mapped GPIO in top-level FPGA fabric */
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size_t temp_io_index = io_location_map.io_index(
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile,
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module_io_port.get_name());
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile,
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module_io_port.get_name());
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/* Bypass invalid index (not mapped to this GPIO port) */
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if (size_t(-1) == temp_io_index) {
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@ -413,28 +412,28 @@ void print_verilog_testbench_connect_fpga_ios(
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if (ModuleManager::MODULE_GPIO_PORT ==
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module_manager.port_type(top_module, module_io_port_id)) {
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mapped_module_io_info =
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std::make_pair(module_io_port_id, temp_io_index);
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std::make_pair(module_io_port_id, temp_io_index);
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break;
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}
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/* If this is an INPAD, we can use an GPIN port (if available) */
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if (atom_block_type_to_module_port_type[atom_ctx.nlist.block_type(
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atom_blk)] ==
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atom_blk)] ==
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module_manager.port_type(top_module, module_io_port_id)) {
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mapped_module_io_info =
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std::make_pair(module_io_port_id, temp_io_index);
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std::make_pair(module_io_port_id, temp_io_index);
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break;
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}
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}
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/* We must find a valid one */
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VTR_ASSERT(true == module_manager.valid_module_port_id(
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top_module, mapped_module_io_info.first));
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top_module, mapped_module_io_info.first));
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VTR_ASSERT(size_t(-1) != mapped_module_io_info.second);
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/* Ensure that IO index is in range */
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BasicPort module_mapped_io_port =
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module_manager.module_port(top_module, mapped_module_io_info.first);
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module_manager.module_port(top_module, mapped_module_io_info.first);
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size_t io_index = mapped_module_io_info.second;
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/* Set the port pin index */
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@ -484,24 +483,24 @@ void print_verilog_testbench_connect_fpga_ios(
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benchmark_io_port.set_name(block_name);
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} else {
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benchmark_io_port.set_name(
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std::string(block_name + io_input_port_name_postfix));
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std::string(block_name + io_input_port_name_postfix));
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}
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print_verilog_comment(
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fp, std::string("----- Blif Benchmark input " + block_name +
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" is mapped to FPGA IOPAD " +
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module_mapped_io_port.get_name() + "[" +
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std::to_string(io_index) + "] -----"));
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fp, std::string("----- Blif Benchmark input " + block_name +
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" is mapped to FPGA IOPAD " +
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module_mapped_io_port.get_name() + "[" +
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std::to_string(io_index) + "] -----"));
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print_verilog_wire_connection(fp, module_mapped_io_port,
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benchmark_io_port, false);
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} else {
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VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
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benchmark_io_port.set_name(
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std::string(block_name + io_output_port_name_postfix));
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std::string(block_name + io_output_port_name_postfix));
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print_verilog_comment(
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fp, std::string("----- Blif Benchmark output " + block_name +
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" is mapped to FPGA IOPAD " +
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module_mapped_io_port.get_name() + "[" +
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std::to_string(io_index) + "] -----"));
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fp, std::string("----- Blif Benchmark output " + block_name +
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" is mapped to FPGA IOPAD " +
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module_mapped_io_port.get_name() + "[" +
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std::to_string(io_index) + "] -----"));
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print_verilog_wire_connection(fp, benchmark_io_port,
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module_mapped_io_port, false);
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}
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@ -515,7 +514,7 @@ void print_verilog_testbench_connect_fpga_ios(
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/* Wire the unused iopads to a constant */
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print_verilog_comment(
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fp, std::string("----- Wire unused FPGA I/Os to constants -----"));
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fp, std::string("----- Wire unused FPGA I/Os to constants -----"));
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for (const ModulePortId& module_io_port_id : module_io_ports) {
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for (size_t io_index = 0; io_index < io_used[module_io_port_id].size();
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++io_index) {
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@ -532,7 +531,7 @@ void print_verilog_testbench_connect_fpga_ios(
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/* Wire to a contant */
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BasicPort module_unused_io_port =
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module_manager.module_port(top_module, module_io_port_id);
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module_manager.module_port(top_module, module_io_port_id);
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/* Set the port pin index */
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module_unused_io_port.set_name(module_unused_io_port.get_name() +
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net_name_postfix);
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@ -556,16 +555,16 @@ void print_verilog_testbench_connect_fpga_ios(
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* Note that: these codes are tuned for Icarus simulator!!!
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*******************************************************************/
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void print_verilog_timeout_and_vcd(
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std::fstream& fp, const std::string& module_name,
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const std::string& vcd_fname,
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const std::string& simulation_start_counter_name,
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const std::string& error_counter_name, const float& simulation_time,
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const bool& no_self_checking) {
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std::fstream& fp, const std::string& module_name,
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const std::string& vcd_fname,
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const std::string& simulation_start_counter_name,
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const std::string& error_counter_name, const float& simulation_time,
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const bool& no_self_checking) {
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/* Validate the file stream */
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valid_file_stream(fp);
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print_verilog_comment(
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fp, std::string("----- Begin output waveform to VCD file-------"));
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fp, std::string("----- Begin output waveform to VCD file-------"));
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fp << "\tinitial begin" << std::endl;
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fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl;
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@ -573,7 +572,7 @@ void print_verilog_timeout_and_vcd(
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fp << "\tend" << std::endl;
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print_verilog_comment(
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fp, std::string("----- END output waveform to VCD file -------"));
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fp, std::string("----- END output waveform to VCD file -------"));
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/* Add an empty line as splitter */
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fp << std::endl;
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@ -590,8 +589,8 @@ void print_verilog_timeout_and_vcd(
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fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl;
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fp << "\t$display(\"Simulation start\");" << std::endl;
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print_verilog_comment(
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fp,
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std::string("----- Can be changed by the user for his/her need -------"));
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fp,
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std::string("----- Can be changed by the user for his/her need -------"));
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fp << "\t#" << std::setprecision(10) << simulation_time << std::endl;
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if (!no_self_checking) {
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@ -620,8 +619,8 @@ void print_verilog_timeout_and_vcd(
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* Assume this is a single clock benchmark
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*******************************************************************/
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std::vector<BasicPort> generate_verilog_testbench_clock_port(
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const std::vector<std::string>& clock_port_names,
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const std::string& default_clock_name) {
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const std::vector<std::string>& clock_port_names,
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const std::string& default_clock_name) {
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std::vector<BasicPort> clock_ports;
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if (0 == clock_port_names.size()) {
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clock_ports.push_back(BasicPort(default_clock_name, 1));
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@ -640,23 +639,23 @@ std::vector<BasicPort> generate_verilog_testbench_clock_port(
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* Restriction: this function only supports single clock benchmarks!
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*******************************************************************/
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void print_verilog_testbench_check(
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std::fstream& fp, const std::string& simulation_start_counter_name,
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const std::string& benchmark_port_postfix,
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const std::string& fpga_port_postfix,
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const std::string& check_flag_port_postfix,
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const std::string& config_done_name, const std::string& error_counter_name,
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const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
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const std::vector<std::string>& clock_port_names,
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const std::string& default_clock_name) {
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std::fstream& fp, const std::string& simulation_start_counter_name,
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const std::string& benchmark_port_postfix,
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const std::string& fpga_port_postfix,
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const std::string& check_flag_port_postfix,
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const std::string& config_done_name, const std::string& error_counter_name,
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const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation,
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const std::vector<std::string>& clock_port_names,
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const std::string& default_clock_name) {
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/* Validate the file stream */
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valid_file_stream(fp);
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/* Add output autocheck */
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print_verilog_comment(
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fp, std::string("----- Begin checking output vectors -------"));
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fp, std::string("----- Begin checking output vectors -------"));
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std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(
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clock_port_names, default_clock_name);
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std::vector<BasicPort> clock_ports =
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generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
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print_verilog_comment(fp,
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std::string("----- Skip the first falling edge of "
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@ -766,21 +765,21 @@ void print_verilog_testbench_check(
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* but be only used as a synchronizer in verification
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*******************************************************************/
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void print_verilog_testbench_clock_stimuli(
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std::fstream& fp, const PinConstraints& pin_constraints,
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const SimulationSetting& simulation_parameters,
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const std::vector<BasicPort>& clock_ports) {
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std::fstream& fp, const PinConstraints& pin_constraints,
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const SimulationSetting& simulation_parameters,
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const std::vector<BasicPort>& clock_ports) {
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/* Validate the file stream */
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valid_file_stream(fp);
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for (const BasicPort& clock_port : clock_ports) {
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print_verilog_comment(fp, std::string("----- Clock '") +
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clock_port.get_name() +
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std::string("' Initialization -------"));
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clock_port.get_name() +
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std::string("' Initialization -------"));
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/* Find the corresponding clock frequency from the simulation parameters */
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float clk_freq_to_use =
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(0.5 / simulation_parameters.default_operating_clock_frequency()) /
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VERILOG_SIM_TIMESCALE;
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(0.5 / simulation_parameters.default_operating_clock_frequency()) /
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VERILOG_SIM_TIMESCALE;
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/* Check pin constraints to see if this clock is constrained to a specific
|
||||
* pin If constrained,
|
||||
* - connect this clock to default values if it is set to be OPEN
|
||||
|
|
@ -802,8 +801,8 @@ void print_verilog_testbench_clock_stimuli(
|
|||
if (pin_constraints.pin(pin_constraint) ==
|
||||
simulation_parameters.clock_port(sim_clock_id)) {
|
||||
clk_freq_to_use =
|
||||
(0.5 / simulation_parameters.clock_frequency(sim_clock_id)) /
|
||||
VERILOG_SIM_TIMESCALE;
|
||||
(0.5 / simulation_parameters.clock_frequency(sim_clock_id)) /
|
||||
VERILOG_SIM_TIMESCALE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -832,15 +831,15 @@ void print_verilog_testbench_clock_stimuli(
|
|||
* For clock signals, please use print_verilog_testbench_clock_stimuli
|
||||
*******************************************************************/
|
||||
void print_verilog_testbench_random_stimuli(
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
|
||||
const FabricGlobalPortInfo& global_ports,
|
||||
const PinConstraints& pin_constraints,
|
||||
const std::vector<std::string>& clock_port_names,
|
||||
const std::string& input_port_postfix,
|
||||
const std::string& check_flag_port_postfix,
|
||||
const std::vector<BasicPort>& clock_ports, const bool& no_self_checking) {
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
|
||||
const FabricGlobalPortInfo& global_ports,
|
||||
const PinConstraints& pin_constraints,
|
||||
const std::vector<std::string>& clock_port_names,
|
||||
const std::string& input_port_postfix,
|
||||
const std::string& check_flag_port_postfix,
|
||||
const std::vector<BasicPort>& clock_ports, const bool& no_self_checking) {
|
||||
/* Validate the file stream */
|
||||
valid_file_stream(fp);
|
||||
|
||||
|
|
@ -876,8 +875,8 @@ void print_verilog_testbench_random_stimuli(
|
|||
* fabric because their stimulus cannot be random
|
||||
*/
|
||||
if (true == port_is_fabric_global_reset_port(
|
||||
global_ports, module_manager, module_name_map,
|
||||
pin_constraints.net_pin(block_name))) {
|
||||
global_ports, module_manager, module_name_map,
|
||||
pin_constraints.net_pin(block_name))) {
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -960,8 +959,8 @@ void print_verilog_testbench_random_stimuli(
|
|||
* fabric because their stimulus cannot be random
|
||||
*/
|
||||
if (true == port_is_fabric_global_reset_port(
|
||||
global_ports, module_manager, module_name_map,
|
||||
pin_constraints.net_pin(block_name))) {
|
||||
global_ports, module_manager, module_name_map,
|
||||
pin_constraints.net_pin(block_name))) {
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -986,14 +985,14 @@ void print_verilog_testbench_random_stimuli(
|
|||
* same input vectors
|
||||
*******************************************************************/
|
||||
void print_verilog_testbench_shared_input_ports(
|
||||
std::fstream& fp, const ModuleManager& module_manager,
|
||||
const ModuleNameMap& module_name_map,
|
||||
const FabricGlobalPortInfo& global_ports,
|
||||
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::vector<std::string>& clock_port_names,
|
||||
const bool& include_clock_ports,
|
||||
const std::string& shared_input_port_postfix, const bool& use_reg_port) {
|
||||
std::fstream& fp, const ModuleManager& module_manager,
|
||||
const ModuleNameMap& module_name_map,
|
||||
const FabricGlobalPortInfo& global_ports,
|
||||
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::vector<std::string>& clock_port_names,
|
||||
const bool& include_clock_ports, const std::string& shared_input_port_postfix,
|
||||
const bool& use_reg_port) {
|
||||
/* Validate the file stream */
|
||||
valid_file_stream(fp);
|
||||
|
||||
|
|
@ -1025,8 +1024,8 @@ void print_verilog_testbench_shared_input_ports(
|
|||
BasicPort input_port(block_name + shared_input_port_postfix, 1);
|
||||
/* For global ports, use wires; otherwise, use registers*/
|
||||
if (false == port_is_fabric_global_reset_port(
|
||||
global_ports, module_manager, module_name_map,
|
||||
pin_constraints.net_pin(block_name))) {
|
||||
global_ports, module_manager, module_name_map,
|
||||
pin_constraints.net_pin(block_name))) {
|
||||
if (use_reg_port) {
|
||||
fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";"
|
||||
<< std::endl;
|
||||
|
|
@ -1050,9 +1049,9 @@ void print_verilog_testbench_shared_input_ports(
|
|||
* 2. the output ports (wires) for FPGA fabric
|
||||
*******************************************************************/
|
||||
void print_verilog_testbench_shared_fpga_output_ports(
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::string& fpga_output_port_postfix) {
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::string& fpga_output_port_postfix) {
|
||||
/* Validate the file stream */
|
||||
valid_file_stream(fp);
|
||||
|
||||
|
|
@ -1090,9 +1089,9 @@ void print_verilog_testbench_shared_fpga_output_ports(
|
|||
* 2. the output ports (wires) for benchmark instance
|
||||
*******************************************************************/
|
||||
void print_verilog_testbench_shared_benchmark_output_ports(
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::string& benchmark_output_port_postfix) {
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::string& benchmark_output_port_postfix) {
|
||||
/* Validate the file stream */
|
||||
valid_file_stream(fp);
|
||||
|
||||
|
|
@ -1114,7 +1113,7 @@ void print_verilog_testbench_shared_benchmark_output_ports(
|
|||
|
||||
/* Each logical block assumes a single-width port */
|
||||
BasicPort output_port(
|
||||
std::string(block_name + benchmark_output_port_postfix), 1);
|
||||
std::string(block_name + benchmark_output_port_postfix), 1);
|
||||
fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";"
|
||||
<< std::endl;
|
||||
}
|
||||
|
|
@ -1133,15 +1132,15 @@ void print_verilog_testbench_shared_benchmark_output_ports(
|
|||
* same input vectors
|
||||
*******************************************************************/
|
||||
void print_verilog_testbench_shared_check_flags(
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::string& check_flag_port_postfix) {
|
||||
std::fstream& fp, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::string& check_flag_port_postfix) {
|
||||
/* Validate the file stream */
|
||||
valid_file_stream(fp);
|
||||
|
||||
/* Instantiate register for output comparison */
|
||||
print_verilog_comment(
|
||||
fp, std::string("----- Output vectors checking flags -------"));
|
||||
fp, std::string("----- Output vectors checking flags -------"));
|
||||
for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
|
||||
/* We care only those logic blocks which are output I/Os */
|
||||
if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
|
||||
|
|
@ -1176,30 +1175,30 @@ void print_verilog_testbench_shared_check_flags(
|
|||
* same input vectors
|
||||
*******************************************************************/
|
||||
void print_verilog_testbench_shared_ports(
|
||||
std::fstream& fp, const ModuleManager& module_manager,
|
||||
const ModuleNameMap& module_name_map,
|
||||
const FabricGlobalPortInfo& global_ports,
|
||||
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::vector<std::string>& clock_port_names,
|
||||
const std::string& shared_input_port_postfix,
|
||||
const std::string& benchmark_output_port_postfix,
|
||||
const std::string& fpga_output_port_postfix,
|
||||
const std::string& check_flag_port_postfix, const bool& no_self_checking) {
|
||||
std::fstream& fp, const ModuleManager& module_manager,
|
||||
const ModuleNameMap& module_name_map,
|
||||
const FabricGlobalPortInfo& global_ports,
|
||||
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
|
||||
const VprNetlistAnnotation& netlist_annotation,
|
||||
const std::vector<std::string>& clock_port_names,
|
||||
const std::string& shared_input_port_postfix,
|
||||
const std::string& benchmark_output_port_postfix,
|
||||
const std::string& fpga_output_port_postfix,
|
||||
const std::string& check_flag_port_postfix, const bool& no_self_checking) {
|
||||
print_verilog_testbench_shared_input_ports(
|
||||
fp, module_manager, module_name_map, global_ports, pin_constraints,
|
||||
atom_ctx, netlist_annotation, clock_port_names, false,
|
||||
shared_input_port_postfix, true);
|
||||
fp, module_manager, module_name_map, global_ports, pin_constraints,
|
||||
atom_ctx, netlist_annotation, clock_port_names, false,
|
||||
shared_input_port_postfix, true);
|
||||
|
||||
print_verilog_testbench_shared_fpga_output_ports(
|
||||
fp, atom_ctx, netlist_annotation, fpga_output_port_postfix);
|
||||
fp, atom_ctx, netlist_annotation, fpga_output_port_postfix);
|
||||
|
||||
if (no_self_checking) {
|
||||
return;
|
||||
}
|
||||
|
||||
print_verilog_testbench_shared_benchmark_output_ports(
|
||||
fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix);
|
||||
fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix);
|
||||
|
||||
print_verilog_testbench_shared_check_flags(fp, atom_ctx, netlist_annotation,
|
||||
check_flag_port_postfix);
|
||||
|
|
@ -1214,11 +1213,11 @@ void print_verilog_testbench_shared_ports(
|
|||
* in the graph of modules
|
||||
*******************************************************************/
|
||||
static void rec_print_verilog_testbench_primitive_module_signal_initialization(
|
||||
std::fstream& fp, const std::string& hie_path,
|
||||
const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
|
||||
const std::vector<CircuitPortId>& circuit_input_ports,
|
||||
const ModuleManager& module_manager, const ModuleId& parent_module,
|
||||
const ModuleId& primitive_module, const bool& deposit_random_values) {
|
||||
std::fstream& fp, const std::string& hie_path,
|
||||
const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
|
||||
const std::vector<CircuitPortId>& circuit_input_ports,
|
||||
const ModuleManager& module_manager, const ModuleId& parent_module,
|
||||
const ModuleId& primitive_module, const bool& deposit_random_values) {
|
||||
/* Validate the file stream */
|
||||
valid_file_stream(fp);
|
||||
|
||||
|
|
@ -1236,20 +1235,20 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization(
|
|||
for (const size_t& child_instance :
|
||||
module_manager.child_module_instances(parent_module, child_module)) {
|
||||
std::string instance_name = module_manager.instance_name(
|
||||
parent_module, child_module, child_instance);
|
||||
parent_module, child_module, child_instance);
|
||||
/* Use default instanec name if not assigned */
|
||||
if (true == instance_name.empty()) {
|
||||
instance_name = generate_instance_name(
|
||||
module_manager.module_name(child_module), child_instance);
|
||||
module_manager.module_name(child_module), child_instance);
|
||||
}
|
||||
|
||||
std::string child_hie_path = hie_path + "." + instance_name;
|
||||
|
||||
if (child_module != primitive_module) {
|
||||
rec_print_verilog_testbench_primitive_module_signal_initialization(
|
||||
fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports,
|
||||
module_manager, child_module, primitive_module,
|
||||
deposit_random_values);
|
||||
fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports,
|
||||
module_manager, child_module, primitive_module,
|
||||
deposit_random_values);
|
||||
} else {
|
||||
/* If the child module is the primitive module,
|
||||
* we output the signal initialization codes for the input ports
|
||||
|
|
@ -1257,7 +1256,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization(
|
|||
VTR_ASSERT_SAFE(child_module == primitive_module);
|
||||
|
||||
print_verilog_comment(
|
||||
fp, std::string("------ BEGIN driver initialization -----"));
|
||||
fp, std::string("------ BEGIN driver initialization -----"));
|
||||
fp << "\tinitial begin" << std::endl;
|
||||
|
||||
for (const auto& input_port : circuit_input_ports) {
|
||||
|
|
@ -1283,7 +1282,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization(
|
|||
|
||||
fp << "\tend" << std::endl;
|
||||
print_verilog_comment(
|
||||
fp, std::string("------ END driver initialization -----"));
|
||||
fp, std::string("------ END driver initialization -----"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1297,9 +1296,9 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization(
|
|||
* - Logic gates (ONLY for MUX2)
|
||||
*******************************************************************/
|
||||
void print_verilog_testbench_signal_initialization(
|
||||
std::fstream& fp, const std::string& top_instance_name,
|
||||
const CircuitLibrary& circuit_lib, const ModuleManager& module_manager,
|
||||
const ModuleId& top_module, const bool& deposit_random_values) {
|
||||
std::fstream& fp, const std::string& top_instance_name,
|
||||
const CircuitLibrary& circuit_lib, const ModuleManager& module_manager,
|
||||
const ModuleId& top_module, const bool& deposit_random_values) {
|
||||
/* Validate the file stream */
|
||||
valid_file_stream(fp);
|
||||
|
||||
|
|
@ -1308,7 +1307,7 @@ void print_verilog_testbench_signal_initialization(
|
|||
|
||||
/* Collect the input ports that require signal initialization */
|
||||
std::map<CircuitModelId, std::vector<CircuitPortId>>
|
||||
signal_init_circuit_ports;
|
||||
signal_init_circuit_ports;
|
||||
|
||||
for (const CircuitModelId& model :
|
||||
circuit_lib.models_by_type(CIRCUIT_MODEL_PASSGATE)) {
|
||||
|
|
@ -1317,7 +1316,7 @@ void print_verilog_testbench_signal_initialization(
|
|||
* which is the first port, i.e., the datapath inputs
|
||||
*/
|
||||
std::vector<CircuitPortId> input_ports =
|
||||
circuit_lib.model_input_ports(model);
|
||||
circuit_lib.model_input_ports(model);
|
||||
VTR_ASSERT(0 < input_ports.size());
|
||||
signal_init_circuit_ports[model].push_back(input_ports[0]);
|
||||
}
|
||||
|
|
@ -1330,7 +1329,7 @@ void print_verilog_testbench_signal_initialization(
|
|||
* which is the first two port, i.e., the datapath inputs
|
||||
*/
|
||||
std::vector<CircuitPortId> input_ports =
|
||||
circuit_lib.model_input_ports(model);
|
||||
circuit_lib.model_input_ports(model);
|
||||
VTR_ASSERT(1 < input_ports.size());
|
||||
signal_init_circuit_ports[model].push_back(input_ports[0]);
|
||||
signal_init_circuit_ports[model].push_back(input_ports[1]);
|
||||
|
|
@ -1349,14 +1348,14 @@ void print_verilog_testbench_signal_initialization(
|
|||
/* Find the module id corresponding to the circuit model from module graph
|
||||
*/
|
||||
ModuleId primitive_module = module_manager.find_module(
|
||||
circuit_lib.model_name(signal_init_circuit_model));
|
||||
circuit_lib.model_name(signal_init_circuit_model));
|
||||
VTR_ASSERT(true == module_manager.valid_module_id(primitive_module));
|
||||
|
||||
/* Find all the instances created by the circuit model across the fabric*/
|
||||
rec_print_verilog_testbench_primitive_module_signal_initialization(
|
||||
fp, top_instance_name, circuit_lib, signal_init_circuit_model,
|
||||
signal_init_circuit_ports.at(signal_init_circuit_model), module_manager,
|
||||
top_module, primitive_module, deposit_random_values);
|
||||
fp, top_instance_name, circuit_lib, signal_init_circuit_model,
|
||||
signal_init_circuit_ports.at(signal_init_circuit_model), module_manager,
|
||||
top_module, primitive_module, deposit_random_values);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue