From a9e5e1af89f420945d19726cc00d2c5053e5456c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 May 2023 18:49:57 -0700 Subject: [PATCH] [core] now fabric netlist include mock wrapper --- .../base/openfpga_verilog_command_template.h | 5 +++ openfpga/src/base/openfpga_verilog_template.h | 12 +++--- openfpga/src/fpga_verilog/verilog_api.cpp | 33 +++++++++++---- openfpga/src/fpga_verilog/verilog_api.h | 4 +- .../verilog_auxiliary_netlists.cpp | 42 +++++++++++++++++++ .../fpga_verilog/verilog_auxiliary_netlists.h | 4 ++ .../verilog_mock_fpga_wrapper.cpp | 10 ++--- .../fpga_verilog/verilog_mock_fpga_wrapper.h | 10 ++--- 8 files changed, 91 insertions(+), 29 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index c1b7e6c64..010b73802 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -281,6 +281,11 @@ ShellCommandId add_write_mock_fpga_wrapper_command_template( shell_cmd.set_option_short_name(bgf_opt, "bgf"); shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); + /* Add an option '--use_relative_path' */ + shell_cmd.add_option( + "use_relative_path", false, + "Force to use relative path in netlists when including other netlists"); + /* add an option '--explicit_port_mapping' */ shell_cmd.add_option("explicit_port_mapping", false, "use explicit port mapping in verilog netlists"); diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 99d8df2ad..a25ce81c1 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -220,6 +220,7 @@ int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd, CommandOptionId opt_bgf = cmd.option("bus_group_file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_use_relative_path = cmd.option("use_relative_path"); CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); CommandOptionId opt_verbose = cmd.option("verbose"); @@ -231,6 +232,8 @@ int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd, options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); options.set_explicit_port_mapping( cmd_context.option_enable(cmd, opt_explicit_port_mapping)); + options.set_use_relative_path( + cmd_context.option_enable(cmd, opt_use_relative_path)); options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); @@ -254,11 +257,10 @@ int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd, } return fpga_verilog_mock_fpga_wrapper( - openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(), - g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group, - openfpga_ctx.io_location_map(), openfpga_ctx.fabric_global_port_info(), - openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib, - openfpga_ctx.arch().config_protocol, options); + openfpga_ctx.module_graph(), g_vpr_ctx.atom(), g_vpr_ctx.placement(), + pin_constraints, bus_group, openfpga_ctx.io_location_map(), + openfpga_ctx.fabric_global_port_info(), + openfpga_ctx.vpr_netlist_annotation(), options); } /******************************************************************** diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index aaea119cb..4bc5e6ced 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -229,13 +229,11 @@ int fpga_verilog_preconfigured_fabric_wrapper( * which encapsulate the application HDL into a mock FPGA module ********************************************************************/ int fpga_verilog_mock_fpga_wrapper( - const ModuleManager &module_manager, - const BitstreamManager &bitstream_manager, const AtomContext &atom_ctx, + const ModuleManager &module_manager, const AtomContext &atom_ctx, const PlacementContext &place_ctx, const PinConstraints &pin_constraints, const BusGroup &bus_group, const IoLocationMap &io_location_map, const FabricGlobalPortInfo &fabric_global_port_info, const VprNetlistAnnotation &netlist_annotation, - const CircuitLibrary &circuit_lib, const ConfigProtocol &config_protocol, const VerilogTestbenchOption &options) { vtr::ScopedStartFinishTimer timer( "Write a wrapper module to mock a mapped FPGA fabric\n"); @@ -246,19 +244,36 @@ int fpga_verilog_mock_fpga_wrapper( int status = CMD_EXEC_SUCCESS; + NetlistManager netlist_manager; + /* Create directories */ create_directory(src_dir_path); /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and * pre-configured testbench for verification */ - std::string netlist_file_path = - src_dir_path + + std::string netlist_file_name = generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX)); + std::string netlist_file_path = src_dir_path + netlist_file_name; status = print_verilog_mock_fpga_wrapper( - module_manager, bitstream_manager, config_protocol, circuit_lib, - fabric_global_port_info, atom_ctx, place_ctx, pin_constraints, bus_group, - io_location_map, netlist_annotation, netlist_name, netlist_file_path, - options); + module_manager, fabric_global_port_info, atom_ctx, place_ctx, + pin_constraints, bus_group, io_location_map, netlist_annotation, + netlist_name, netlist_file_path, options); + + /* Add fname to the netlist name list */ + NetlistId nlist_id = NetlistId::INVALID(); + if (options.use_relative_path()) { + nlist_id = netlist_manager.add_netlist(netlist_file_name); + } else { + nlist_id = netlist_manager.add_netlist(netlist_file_path); + } + VTR_ASSERT(nlist_id); + netlist_manager.set_netlist_type(nlist_id, + NetlistManager::TOP_MODULE_NETLIST); + + /* Generate an netlist including all the fabric-related netlists */ + print_verilog_mock_fabric_include_netlist(netlist_manager, src_dir_path, + options.use_relative_path(), + options.time_stamp()); return status; } diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index c680a6251..914e58d70 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -69,13 +69,11 @@ int fpga_verilog_preconfigured_fabric_wrapper( const VerilogTestbenchOption& options); int fpga_verilog_mock_fpga_wrapper( - const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, const AtomContext& atom_ctx, + const ModuleManager& module_manager, const AtomContext& atom_ctx, const PlacementContext& place_ctx, const PinConstraints& pin_constraints, const BusGroup& bus_group, const IoLocationMap& io_location_map, const FabricGlobalPortInfo& fabric_global_port_info, const VprNetlistAnnotation& netlist_annotation, - const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const VerilogTestbenchOption& options); int fpga_verilog_preconfigured_testbench( diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index aa600ddba..a19ee9446 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -23,6 +23,48 @@ namespace openfpga { * Local constant variables *******************************************************************/ +/******************************************************************** + * Print a file that includes all the fabric netlists + * that have been generated and user-defined. + * This does NOT include any testbenches! + * Some netlists are open to compile under specific preprocessing flags + *******************************************************************/ +void print_verilog_mock_fabric_include_netlist( + const NetlistManager& netlist_manager, const std::string& src_dir_path, + const bool& use_relative_path, const bool& include_time_stamp) { + /* If we force the use of relative path, the src dir path should NOT be + * included in any output */ + std::string src_dir = src_dir_path; + if (use_relative_path) { + src_dir.clear(); + } + std::string verilog_fpath = + src_dir_path + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_stream(verilog_fpath.c_str(), fp); + + /* Print the title */ + print_verilog_file_header(fp, std::string("Mock Fabric Netlist Summary"), + include_time_stamp); + + /* Include FPGA top module */ + print_verilog_comment( + fp, std::string("------ Include fabric top-level netlists -----")); + for (const NetlistId& nlist_id : + netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) { + print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id)); + } + fp << std::endl; + + /* Close the file stream */ + fp.close(); +} + /******************************************************************** * Print a file that includes all the fabric netlists * that have been generated and user-defined. diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h index 553c8c3a4..493f2c4af 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h @@ -18,6 +18,10 @@ /* begin namespace openfpga */ namespace openfpga { +void print_verilog_mock_fabric_include_netlist( + const NetlistManager& netlist_manager, const std::string& src_dir_path, + const bool& use_relative_path, const bool& include_time_stamp); + void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager, const std::string& src_dir_path, const CircuitLibrary& circuit_lib, diff --git a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp index 9fa67eaff..6389ca5d6 100644 --- a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp +++ b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp @@ -286,12 +286,10 @@ static void print_verilog_mock_fpga_wrapper_connect_ios( *application HDL (supposed to be implemented on FPGA). *******************************************************************/ int print_verilog_mock_fpga_wrapper( - const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, - const FabricGlobalPortInfo& global_ports, const AtomContext& atom_ctx, - const PlacementContext& place_ctx, const PinConstraints& pin_constraints, - const BusGroup& bus_group, const IoLocationMap& io_location_map, + const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const AtomContext& atom_ctx, const PlacementContext& place_ctx, + const PinConstraints& pin_constraints, const BusGroup& bus_group, + const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, const std::string& verilog_fname, const VerilogTestbenchOption& options) { diff --git a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.h b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.h index 503fd679f..62f2f5d71 100644 --- a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.h +++ b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.h @@ -27,12 +27,10 @@ namespace openfpga { int print_verilog_mock_fpga_wrapper( - const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, - const FabricGlobalPortInfo& global_ports, const AtomContext& atom_ctx, - const PlacementContext& place_ctx, const PinConstraints& pin_constraints, - const BusGroup& bus_group, const IoLocationMap& io_location_map, + const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, + const AtomContext& atom_ctx, const PlacementContext& place_ctx, + const PinConstraints& pin_constraints, const BusGroup& bus_group, + const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, const std::string& verilog_fname, const VerilogTestbenchOption& options);