diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml
new file mode 100644
index 000000000..cd12856c5
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml
@@ -0,0 +1,253 @@
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12 5e-12
+
+
+ 10e-12 5e-12 5e-12
+
+
+
+
+
+
+
+
+
+
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diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml
new file mode 100644
index 000000000..e9a81bfd8
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml
@@ -0,0 +1,333 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12 5e-12
+
+
+ 10e-12 5e-12 5e-12
+
+
+
+
+
+
+
+
+
+
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diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
index 612249a15..5c155b5b9 100644
--- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
@@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v
index 9a5dfd26e..6491d7870 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v
@@ -60,15 +60,15 @@ endmodule
//-----------------------------
// 18-bit multiplier
//-----------------------------
-module mult_18(
- input [0:17] A,
- input [0:17] B,
- output [0:35] Y
-);
+// module mult_18(
+// input [0:17] A,
+// input [0:17] B,
+// output [0:35] Y
+// );
-assign Y = A * B;
+// assign Y = A * B;
-endmodule
+// endmodule
//-----------------------------
// Native D-type flip-flop
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml
new file mode 100644
index 000000000..5351486bc
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml
@@ -0,0 +1,620 @@
+
+
+
+
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+
+
+
+
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+
+
+
+
+
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+
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+ 1 1 1 1 1
+ 1 1 1 1
+
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+ 235e-12
+ 235e-12
+ 235e-12
+
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+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
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+
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
new file mode 100644
index 000000000..081680026
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
@@ -0,0 +1,1223 @@
+
+
+
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+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+
+
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+
+ clb.clk clb.reset clb.set
+ clb.cin
+ clb.O[9:0] clb.I[19:0]
+ clb.cout clb.O[19:10] clb.I[39:20]
+
+
+
+
+
+
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+
+
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+
+
+
+ memory.clk
+
+ memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]
+ memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4]
+
+
+
+
+
+
+
+
+
+
+
+
+
+ mult_18.b[0:4] mult_18.b[5:17] mult_18.out[18:35]
+
+ mult_18.a[0:4] mult_18.a[5:17] mult_18.out[0:17]
+
+
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+ 1 1 1 1 1
+ 1 1 1 1
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