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[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``

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tangxifan 2021-06-30 15:29:13 -06:00
parent 83d177b13b
commit a898537474
1 changed files with 0 additions and 65 deletions
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65
openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v
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@ -1,65 +0,0 @@
/* Generated by Yosys 0.9+2406 (git sha1 3a9968de, gcc 8.4.0 -fPIC -Os) */
module adder_8(\a[0] , \a[1] , \a[2] , \a[3] , \a[4] , \a[5] , \a[6] , \a[7] , \b[0] , \b[1] , \b[2] , \b[3] , \b[4] , \b[5] , \b[6] , \b[7] , cin, cout, \sum[0] , \sum[1] , \sum[2] , \sum[3] , \sum[4] , \sum[5] , \sum[6] , \sum[7] );
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
input \a[0] ;
input \a[1] ;
input \a[2] ;
input \a[3] ;
input \a[4] ;
input \a[5] ;
input \a[6] ;
input \a[7] ;
input \b[0] ;
input \b[1] ;
input \b[2] ;
input \b[3] ;
input \b[4] ;
input \b[5] ;
input \b[6] ;
input \b[7] ;
input cin;
output cout;
output \sum[0] ;
output \sum[1] ;
output \sum[2] ;
output \sum[3] ;
output \sum[4] ;
output \sum[5] ;
output \sum[6] ;
output \sum[7] ;
assign cout = 8'h8e >> { _00_, \a[7] , \b[7] };
assign _08_ = 4'h8 >> { \a[5] , \b[5] };
assign \sum[0] = 8'h96 >> { \a[0] , \b[0] , cin };
assign \sum[1] = 8'h69 >> { _05_, \a[1] , \b[1] };
assign \sum[2] = 16'h6a56 >> { _05_, \a[1] , \b[1] , _04_ };
assign \sum[3] = 16'h9996 >> { _03_, _06_, \a[3] , \b[3] };
assign \sum[4] = 8'h69 >> { _02_, \a[4] , \b[4] };
assign \sum[5] = 8'h69 >> { _09_, \a[5] , \b[5] };
assign _09_ = 8'h71 >> { _02_, \a[4] , \b[4] };
assign \sum[6] = 16'h9996 >> { _01_, _08_, \a[6] , \b[6] };
assign \sum[7] = 8'h69 >> { _00_, \a[7] , \b[7] };
assign _00_ = 16'h011f >> { \a[6] , \b[6] , _01_, _08_ };
assign _01_ = 16'h4054 >> { _02_, \a[4] , \b[4] , _07_ };
assign _02_ = 16'h011f >> { \a[3] , \b[3] , _03_, _06_ };
assign _03_ = 16'h80a8 >> { _05_, \a[1] , \b[1] , _04_ };
assign _04_ = 4'h6 >> { \a[2] , \b[2] };
assign _05_ = 8'h17 >> { \a[0] , \b[0] , cin };
assign _06_ = 4'h8 >> { \a[2] , \b[2] };
assign _07_ = 4'h1 >> { \a[5] , \b[5] };
assign _10_ = 1'h0;
assign _11_ = 1'h1;
assign _12_ = 1'hx;
endmodule