From a85a6f1674171909caceb485295f7a2cd7f10380 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Jul 2024 17:57:10 -0700 Subject: [PATCH] [core] code format --- .../src/base/clock_network.cpp | 6 ++++-- .../src/io/write_xml_clock_network.cpp | 15 +++++++------ .../src/utils/clock_network_utils.cpp | 21 +++++++++++++------ .../src/base/openfpga_read_arch_template.h | 9 ++++---- 4 files changed, 33 insertions(+), 18 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 440870f29..2889876ab 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -863,9 +863,11 @@ bool ClockNetwork::validate_tree_taps() const { for (ClockTreeId tree_id : trees()) { for (ClockTapId tap_id : tree_taps(tree_id)) { /* The from pin name should match the global port */ - if (!tree_global_port(tree_id).mergeable(tap_from_port(tap_id)) || !tree_global_port(tree_id).contained(tap_from_port(tap_id))) { + if (!tree_global_port(tree_id).mergeable(tap_from_port(tap_id)) || + !tree_global_port(tree_id).contained(tap_from_port(tap_id))) { VTR_LOG_ERROR( - "Tap point from_port '%s' is not part of the global port '%s' of tree '%s'\n", + "Tap point from_port '%s' is not part of the global port '%s' of " + "tree '%s'\n", tap_from_port(tap_id).to_verilog_string().c_str(), tree_global_port(tree_id).to_verilog_string().c_str(), tree_name(tree_id).c_str()); diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index fbdea521d..1e03bc0ba 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -34,8 +34,9 @@ static int write_xml_clock_tree_taps(std::fstream& fp, case ClockNetwork::e_tap_type::ALL: { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); fp << "/>" @@ -45,8 +46,9 @@ static int write_xml_clock_tree_taps(std::fstream& fp, case ClockNetwork::e_tap_type::SINGLE: { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, @@ -60,8 +62,9 @@ static int write_xml_clock_tree_taps(std::fstream& fp, case ClockNetwork::e_tap_type::REGION: { openfpga::write_tab_to_file(fp, 4); fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << ""; - write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, - clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN, + clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, clk_ntwk.tap_to_port(tap_id).c_str()); write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index 449352403..6f78b26fe 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -97,7 +97,8 @@ int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, } /** Check for each global ports in tile annotation - * If a clock tree is required for a global port, the global port name define in the tile annotation should match the one in clock clock + * If a clock tree is required for a global port, the global port name define + * in the tile annotation should match the one in clock clock */ int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, const TileAnnotation& tile_annotation) { @@ -106,16 +107,24 @@ int check_clock_network_tile_annotation(const ClockNetwork& clk_ntwk, continue; } std::string gport_name = tile_annotation.global_port_name(gport_id); - std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(gport_id); + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(gport_id); ClockTreeId clk_tree_id = clk_ntwk.find_tree(clk_tree_name); if (!clk_ntwk.valid_tree_id(clk_tree_id)) { - VTR_LOG_ERROR("Invalid clock tree name '%s' defined for global port '%s' in tile annotation! Must be a valid name defined in the clock network description!\n", - clk_tree_name.c_str(), gport_name.c_str()); + VTR_LOG_ERROR( + "Invalid clock tree name '%s' defined for global port '%s' in tile " + "annotation! Must be a valid name defined in the clock network " + "description!\n", + clk_tree_name.c_str(), gport_name.c_str()); return CMD_EXEC_FATAL_ERROR; } if (clk_ntwk.tree_global_port(clk_tree_id).get_name() != gport_name) { - VTR_LOG_ERROR("Global port '%s' of clock tree name '%s' must match the name of assoicated global port '%s' in tile annotation! Must be a valid name defined in the clock network description!\n", - clk_ntwk.tree_global_port(clk_tree_id).to_verilog_string().c_str(), clk_tree_name.c_str(), gport_name.c_str()); + VTR_LOG_ERROR( + "Global port '%s' of clock tree name '%s' must match the name of " + "assoicated global port '%s' in tile annotation! Must be a valid name " + "defined in the clock network description!\n", + clk_ntwk.tree_global_port(clk_tree_id).to_verilog_string().c_str(), + clk_tree_name.c_str(), gport_name.c_str()); return CMD_EXEC_FATAL_ERROR; } } diff --git a/openfpga/src/base/openfpga_read_arch_template.h b/openfpga/src/base/openfpga_read_arch_template.h index e0dd9dd34..346deae5f 100644 --- a/openfpga/src/base/openfpga_read_arch_template.h +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -246,10 +246,11 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd, VTR_LOG_ERROR("Link clock network to routing architecture failed!"); return CMD_EXEC_FATAL_ERROR; } - if (CMD_EXEC_SUCCESS != - check_clock_network_tile_annotation(openfpga_context.clock_arch(), - openfpga_context.arch().tile_annotations)) { - VTR_LOG_ERROR("Check clock network consistency with tile annotation failed!"); + if (CMD_EXEC_SUCCESS != check_clock_network_tile_annotation( + openfpga_context.clock_arch(), + openfpga_context.arch().tile_annotations)) { + VTR_LOG_ERROR( + "Check clock network consistency with tile annotation failed!"); return CMD_EXEC_FATAL_ERROR; } /* Ensure clean data */