Merge changes from ganesh.
This commit is contained in:
parent
cdb799c59f
commit
a85a1cfb6d
|
@ -193,16 +193,11 @@ jobs:
|
|||
fail-fast: false
|
||||
matrix:
|
||||
config:
|
||||
- name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: basic_reg_test.sh
|
||||
- name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_verilog_reg_test.sh
|
||||
- name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_bitstream_reg_test.sh
|
||||
- name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_sdc_reg_test.sh
|
||||
- name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_spice_reg_test.sh
|
||||
- name: basic_reg_test
|
||||
- name: fpga_verilog_reg_test
|
||||
- name: fpga_bitstream_reg_test
|
||||
- name: fpga_sdc_reg_test
|
||||
- name: fpga_spice_reg_test
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
|
@ -221,12 +216,18 @@ jobs:
|
|||
chmod +x yosys/yosys-config
|
||||
chmod +x yosys/yosys-filterlib
|
||||
chmod +x yosys/yosys-smtbmc
|
||||
- name: ${{matrix.config.name}}
|
||||
- name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
|
||||
shell: bash
|
||||
run: source .github/workflows/${{matrix.config.script}}
|
||||
run: source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh
|
||||
- name: Upload artifact
|
||||
uses: actions/upload-artifact@v2
|
||||
if: ${{ failure() }}
|
||||
with:
|
||||
name: failed_${{matrix.config.name}}_regression_log
|
||||
retention-days: 1
|
||||
path: |
|
||||
openfpga_flow/**/*.log
|
||||
docker_regression_tests:
|
||||
env:
|
||||
OPENFPGA_PATH: /__w/OpenFPGA/OpenFPGA
|
||||
needs: change_detect
|
||||
if: ${{ !fromJSON(needs.change_detect.outputs.source_modified) }}
|
||||
name: Regression tests against master artifacts
|
||||
|
@ -236,32 +237,27 @@ jobs:
|
|||
fail-fast: false
|
||||
matrix:
|
||||
config:
|
||||
- name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: basic_reg_test.sh
|
||||
- name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_verilog_reg_test.sh
|
||||
- name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_bitstream_reg_test.sh
|
||||
- name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_sdc_reg_test.sh
|
||||
- name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)"
|
||||
script: fpga_spice_reg_test.sh
|
||||
- name: basic_reg_test
|
||||
- name: fpga_verilog_reg_test
|
||||
- name: fpga_bitstream_reg_test
|
||||
- name: fpga_sdc_reg_test
|
||||
- name: fpga_spice_reg_test
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
with:
|
||||
submodules: true
|
||||
- name: ${{matrix.config.name}}
|
||||
- name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
|
||||
shell: bash
|
||||
run: |
|
||||
cp /opt/openfpga/abc/abc abc/abc
|
||||
cp /opt/openfpga/ace2/ace ace2/ace
|
||||
cp /opt/openfpga/openfpga/openfpga openfpga/openfpga
|
||||
cp /opt/openfpga/vpr/vpr vpr/vpr
|
||||
cp /opt/openfpga/yosys/yosys yosys/yosys
|
||||
cp /opt/openfpga/yosys/yosys-abc yosys/yosys-abc
|
||||
cp /opt/openfpga/yosys/yosys-config yosys/yosys-config
|
||||
cp /opt/openfpga/yosys/yosys-filterlib yosys/yosys-filterlib
|
||||
cp /opt/openfpga/yosys/yosys-smtbmc yosys/yosys-smtbmc
|
||||
cp -r /opt/openfpga/yosys/share yosys/share
|
||||
source .github/workflows/${{matrix.config.script}}
|
||||
bash .github/workflows/install_dependencies_run.sh
|
||||
python3 -m pip install -r requirements.txt
|
||||
rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. .
|
||||
source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh
|
||||
- name: Upload artifact
|
||||
uses: actions/upload-artifact@v2
|
||||
if: ${{ failure() }}
|
||||
with:
|
||||
name: failed_${{matrix.config.name}}_regression_log
|
||||
retention-days: 1
|
||||
path: openfpga_flow/**/*.log
|
||||
|
|
|
@ -1,2 +1,2 @@
|
|||
apt-get update && apt-get install -y libdatetime-perl iverilog python3-pip git \
|
||||
libc6 libffi6 libgcc1 libreadline7 libstdc++6 libtcl8.6 python3 zlib1g libbz2-1.0
|
||||
apt-get update && apt-get install --no-install-recommends -y libdatetime-perl iverilog python3-pip git \
|
||||
libc6 libffi6 libgcc1 libreadline7 libstdc++6 libtcl8.6 python3 zlib1g libbz2-1.0 rsync
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
FROM ubuntu:18.04
|
||||
ENV DEBIAN_FRONTEND=noninteractive
|
||||
RUN apt-get update && apt-get install software-properties-common -y
|
||||
RUN apt-get update && apt-get install --no-install-recommends software-properties-common -y
|
||||
# 18.04 includes 2.17 but github requires 2.18+ to support submodules.
|
||||
RUN add-apt-repository ppa:git-core/ppa
|
||||
ADD .github/workflows/install_dependencies_run.sh install_dependencies_run.sh
|
||||
RUN bash install_dependencies_run.sh
|
||||
ADD requirements.txt requirements.txt
|
||||
RUN python3 -m pip install -r requirements.txt
|
||||
RUN python3 -m pip install -r requirements.txt
|
|
@ -10,5 +10,5 @@ RUN cd /opt/openfpga && chmod +x abc/abc ace2/ace openfpga/openfpga vpr/vpr yosy
|
|||
COPY openfpga_flow /opt/openfpga/openfpga_flow
|
||||
COPY openfpga.sh /opt/openfpga/openfpga.sh
|
||||
ENV PATH="/opt/openfpga/openfpga:/opt/openfpga/yosys:/opt/openfpga/ace2:/opt/openfpga/abc:/opt/openfpga/vpr:${PATH}"
|
||||
ENV OPENFPGA_PATH="/opt/openfpga:${PATH}"
|
||||
ENV OPENFPGA_PATH="/opt/openfpga"
|
||||
WORKDIR /opt/openfpga
|
||||
|
|
Loading…
Reference in New Issue