From a813c9016b793987e3525542828c4423600c8092 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 4 Jan 2021 17:39:13 -0700
Subject: [PATCH] [Arch] Patch the port name in openfpga arch to avoid
 conflicts with OpenFPGA's reserved words

---
 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml
index 9d8fc8a39..e0fd1f9bb 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml
@@ -143,7 +143,7 @@
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="SE" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="config_done" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
+       <port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="SI" size="1"/>
        <port type="output" prefix="Q" size="1"/>