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Merge pull request #528 from lnis-uofu/tb 

Now the shared input ports in top-level testbench has a dedicated postfix (except clock ports)
This commit is contained in:
tangxifan 2022-02-14 12:17:38 -08:00 committed by GitHub
parent ae5d77b7bc 8d48492ec0
commit a80b2d7882
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 44 additions and 8 deletions
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6
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
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@ -81,6 +81,7 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
clock_port_names,
std::string(),
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
@ -123,8 +124,10 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
std::string(BENCHMARK_INSTANCE_NAME),
std::string(),
std::string(),
std::string(),
prefix_to_remove,
std::string(BENCHMARK_PORT_POSTFIX),
std::vector<std::string>(),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
@ -161,8 +164,10 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
std::string(FPGA_INSTANCE_NAME),
std::string(),
std::string(),
std::string(),
prefix_to_remove,
std::string(FPGA_PORT_POSTFIX),
std::vector<std::string>(),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
@ -345,6 +350,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
global_ports,
pin_constraints,
clock_port_names,
std::string(),
std::string(CHECKFLAG_PORT_POSTFIX),
clock_ports,
options.no_self_checking());

1
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -496,6 +496,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
std::string(),
std::string(),
prefix_to_remove,
std::vector<std::string>(),
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Assign the SRAM model applied to the FPGA fabric */

26
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -78,8 +78,10 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
@ -122,7 +124,12 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) {
fp << "~";
}
fp << block_name;
/* For clock ports, skip postfix */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
fp << block_name;
} else {
fp << block_name << input_port_postfix;
}
if (true == use_explicit_port_map) {
fp << ")";
}
@ -174,6 +181,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::vector<std::string>& clock_port_names,
const size_t& unused_io_value) {
/* Validate the file stream */
valid_file_stream(fp);
@ -277,14 +285,18 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
}
}
/* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1
* In addition, the input and output ports may have different postfix in naming
* due to verification context! Here, we give full customization on naming
*/
BasicPort benchmark_io_port;
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix));
/* If the port is a clock, do not add a postfix */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
benchmark_io_port.set_name(block_name);
} else {
benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix));
}
benchmark_io_port.set_width(1);
print_verilog_comment(fp, std::string("----- Blif Benchmark input " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
@ -580,6 +592,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const std::string& input_port_postfix,
const std::string& check_flag_port_postfix,
const std::vector<BasicPort>& clock_ports,
const bool& no_self_checking) {
@ -617,7 +630,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << block_name << " <= 1'b0;" << std::endl;
fp << "\t\t" << block_name + input_port_postfix << " <= 1'b0;" << std::endl;
}
}
@ -686,7 +699,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << block_name << " <= $random;" << std::endl;
fp << "\t\t" << block_name + input_port_postfix << " <= $random;" << std::endl;
}
}
@ -709,6 +722,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& shared_input_port_postfix,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
@ -736,7 +750,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
}
/* Each logical block assumes a single-width port */
BasicPort input_port(block_name, 1);
BasicPort input_port(block_name + shared_input_port_postfix, 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl;
}

5
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -35,8 +35,10 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
@ -53,6 +55,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::vector<std::string>& clock_port_names,
const size_t& unused_io_value);
void print_verilog_timeout_and_vcd(std::fstream& fp,
@ -89,6 +92,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const std::string& input_port_postfix,
const std::string& check_flag_port_postfix,
const std::vector<BasicPort>& clock_ports,
const bool& no_self_checking);
@ -97,6 +101,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& shared_input_port_postfix,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,

13
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -800,6 +800,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
clock_port_names,
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
@ -927,6 +928,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const std::vector<std::string>& clock_port_names,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -944,8 +946,10 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME),
std::string(),
std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
prefix_to_remove,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
clock_port_names,
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
@ -1810,6 +1814,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const FabricGlobalPortInfo& global_ports,
const PinConstraints& pin_constraints,
const std::string& port_name_postfix,
const std::vector<std::string>& clock_port_names) {
valid_file_stream(fp);
@ -1842,7 +1847,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)));
/* Connect stimuli to greset with an optional inversion, depending on the default value */
BasicPort reset_port(block_name, 1);
BasicPort reset_port(block_name + port_name_postfix, 1);
print_verilog_wire_connection(fp, reset_port,
BasicPort(TOP_TB_RESET_PORT_NAME, 1),
1 == initial_value);
@ -2050,9 +2055,10 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
std::string(),
std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::vector<std::string>(),
clock_port_names,
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Instanciate input benchmark */
@ -2062,6 +2068,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
atom_ctx,
netlist_annotation,
pin_constraints,
clock_port_names,
explicit_port_mapping);
}
@ -2094,6 +2101,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
module_manager,
global_ports,
pin_constraints,
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
clock_port_names);
print_verilog_testbench_random_stimuli(fp, atom_ctx,
netlist_annotation,
@ -2101,6 +2109,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
global_ports,
pin_constraints,
clock_port_names,
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::vector<BasicPort>(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)),
options.no_self_checking());

1
openfpga/src/fpga_verilog/verilog_top_testbench_constants.h
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@ -6,6 +6,7 @@ namespace openfpga {
constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT";
constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT";
constexpr char* TOP_TESTBENCH_SHARED_INPUT_POSTFIX = "_shared_input";
constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark";
constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga";