diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh
index b7a47508e..7b7aad6b0 100755
--- a/.github/workflows/fpga_verilog_reg_test.sh
+++ b/.github/workflows/fpga_verilog_reg_test.sh
@@ -30,7 +30,10 @@ echo -e "Testing Verilog generation with VPR's untileable routing architecture "
 run-task fpga_verilog/untileable --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with hard adder chain in CLBs ";
-run-task fpga_verilog/hard_adder --debug --show_thread_logs
+run-task fpga_verilog/adder/hard_adder --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with soft adder chain in CLBs ";
+run-task fpga_verilog/adder/soft_adder --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with 16k block RAMs ";
 run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs
diff --git a/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf
deleted file mode 100644
index 0764beeb3..000000000
--- a/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf
+++ /dev/null
@@ -1,38 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 20*60
-fpga_flow=vpr_blif
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-external_fabric_key_file=
-
-[ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
-
-[BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
-bench0_chan_width = 300
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-end_flow_with_test=
-vpr_fpga_verilog_formal_verification_top_netlist=