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[FPGA-Bitstream] note limitations

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tangxifan 2022-05-25 18:38:01 +08:00
parent ffac5a66e1
commit a7e87b9432
1 changed files with 5 additions and 0 deletions
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openfpga/src/fpga_bitstream/fabric_bitstream.h
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@ -223,6 +223,11 @@ class FabricBitstream {
* 101x1 -> 10101 -> 21 * 101x1 -> 10101 -> 21
* - bit-x number: which encodes the 'x' bits into a number. For example, * - bit-x number: which encodes the 'x' bits into a number. For example,
* 101x1 -> 00010 -> 2 * 101x1 -> 00010 -> 2
*
* TODO: There is a limitation here, when the length of address vector is more than 64,
* A size_t number overflows (cannot represent any binary number > 64 bit).
* Such thing can entirely happen even in a medium sized FPGA.
* A solution can be use multiple size_t to fit. But clearly, we should not use vector in vector, which causes large memory overhead!
*/ */
vtr::vector<FabricBitId, size_t> bit_address_1bits_; vtr::vector<FabricBitId, size_t> bit_address_1bits_;
vtr::vector<FabricBitId, size_t> bit_address_xbits_; vtr::vector<FabricBitId, size_t> bit_address_xbits_;