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[Arch] Update arch with true embedded I/O definition

This commit is contained in:
tangxifan 2020-11-02 13:29:40 -07:00
parent 65ca53ac98
commit a7e7fa2005
2 changed files with 28 additions and 63 deletions
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19
openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -184,15 +184,20 @@
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIN" prefix="GPIN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/> <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="PAD" lib_name="PAD" size="1" is_global="true" is_io="true" /> <port type="inout" prefix="PAD" lib_name="A" size="1" is_global="true" is_io="true" />
<port type="sram" prefix="DIR" lib_name="DIR" size="1" mode_select="true" circuit_model_name="DFF" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPOUT" prefix="GPOUT" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="inout" prefix="PAD" lib_name="Y" size="1" is_global="true" is_io="true" />
<port type="input" prefix="outpad" lib_name="A" size="1"/>
</circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFF" num_regions="1"/> <organization type="scan_chain" circuit_model_name="DFF" num_regions="1"/>
@ -216,10 +221,8 @@
</direct_connection> </direct_connection>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/> <pb_type name="io[inpad].inpad" circuit_model_name="GPIN"/>
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> <pb_type name="io[outpad].outpad" circuit_model_name="GPOUT"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->

50
openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
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@ -24,15 +24,6 @@
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
@ -227,53 +218,24 @@
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Different from GPIOs, embedded I/O interfaces can afford splitting
If you need to register the I/O, define clocks in the circuit models input and output pin. Therefore, the input pad and output pad are defined
These clocks can be handled in back-end as different blocks
--> -->
<!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation
-->
<mode name="physical" disabled_in_pack="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.