From a6d43beacac9200bb84add0a880e168285155481 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Aug 2023 22:25:52 -0700
Subject: [PATCH] [core] now tile verilog writer supports relative paths

---
 openfpga/src/fpga_verilog/verilog_api.cpp  | 2 +-
 openfpga/src/fpga_verilog/verilog_tile.cpp | 9 ++++++---
 openfpga/src/fpga_verilog/verilog_tile.h   | 1 +
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 68eabe145..921e88176 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -130,7 +130,7 @@ int fpga_fabric_verilog(
   if (!fabric_tile.empty()) {
     status_code = print_verilog_tiles(
       netlist_manager, const_cast<const ModuleManager &>(module_manager),
-      tile_dir_path, fabric_tile, options);
+      tile_dir_path, fabric_tile, std::string(DEFAULT_TILE_DIR_NAME), options);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }
diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp
index 0a3465c4c..400695554 100644
--- a/openfpga/src/fpga_verilog/verilog_tile.cpp
+++ b/openfpga/src/fpga_verilog/verilog_tile.cpp
@@ -27,7 +27,8 @@ namespace openfpga {
 static int print_verilog_tile_module_netlist(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
   const std::string& verilog_dir, const FabricTile& fabric_tile,
-  const FabricTileId& fabric_tile_id, const FabricVerilogOption& options) {
+  const FabricTileId& fabric_tile_id, const std::string& subckt_dir_name,
+  const FabricVerilogOption& options) {
   /* Create a module as the top-level fabric, and add it to the module manager
    */
   vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
@@ -69,10 +70,11 @@ static int print_verilog_tile_module_netlist(
   /* Add fname to the netlist name list */
   NetlistId nlist_id = NetlistId::INVALID();
   if (options.use_relative_path()) {
-    nlist_id = netlist_manager.add_netlist(verilog_fname);
+    nlist_id = netlist_manager.add_netlist(subckt_dir_name + verilog_fname);
   } else {
     nlist_id = netlist_manager.add_netlist(verilog_fpath);
   }
+
   VTR_ASSERT(nlist_id);
   netlist_manager.set_netlist_type(nlist_id,
                                    NetlistManager::TILE_MODULE_NETLIST);
@@ -89,6 +91,7 @@ int print_verilog_tiles(NetlistManager& netlist_manager,
                         const ModuleManager& module_manager,
                         const std::string& verilog_dir,
                         const FabricTile& fabric_tile,
+                        const std::string& subckt_dir_name,
                         const FabricVerilogOption& options) {
   vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric");
 
@@ -98,7 +101,7 @@ int print_verilog_tiles(NetlistManager& netlist_manager,
   for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) {
     status_code = print_verilog_tile_module_netlist(
       netlist_manager, module_manager, verilog_dir, fabric_tile, fabric_tile_id,
-      options);
+      subckt_dir_name, options);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
     }
diff --git a/openfpga/src/fpga_verilog/verilog_tile.h b/openfpga/src/fpga_verilog/verilog_tile.h
index a38886136..03dac11ae 100644
--- a/openfpga/src/fpga_verilog/verilog_tile.h
+++ b/openfpga/src/fpga_verilog/verilog_tile.h
@@ -22,6 +22,7 @@ int print_verilog_tiles(NetlistManager& netlist_manager,
                         const ModuleManager& module_manager,
                         const std::string& verilog_dir,
                         const FabricTile& fabric_tile,
+                        const std::string& subckt_dir_name,
                         const FabricVerilogOption& options);
 
 } /* end namespace openfpga */