riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add security in checking to avoid simulation glitch error

This commit is contained in:
AurelienUoU 2018-12-10 09:46:16 -07:00
parent 7020d9b4b6
commit a69c2e1882
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c
View File

@ -609,8 +609,10 @@ void dump_verilog_top_auto_testbench_check(FILE* fp){
assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type));
if(VPACK_OUTPAD == logical_block[iblock].type){
fprintf(fp, " always@(posedge %s_verification) begin\n", logical_block[iblock].name);
fprintf(fp, " if(%s_verification) begin\n", logical_block[iblock].name);
fprintf(fp, " $display(\"Mismatch on %s_verification\");\n", logical_block[iblock].name);
fprintf(fp, " $finish;\n");
fprintf(fp, " end\n");
fprintf(fp, " end\n\n");
}
}