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[Arch] Bug fix in nature fracturable architecture

This commit is contained in:
tangxifan 2020-11-25 22:48:26 -07:00
parent b8559249dc
commit a60bd4d14a
2 changed files with 75 additions and 27 deletions
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35
openfpga_flow/openfpga_arch/k4_fracNative_N4_40nm_cc_openfpga.xml
View File

@ -199,17 +199,46 @@
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[shared_lut3_lut4].ble4.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4"> <!-- BLE3 LUT uses the frac_LUT4 of physical mode:
Index in CLB of BLE3 LUT -> Index in CLB of physical mode LUT
LUT[0] -> LUT[0]
LUT[1] -> LUT[1]
LUT[2] -> LUT[2]
...
-->
<pb_type name="clb.fle[shared_lut3_lut4].ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 --> <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:2]"/> <port name="in" physical_mode_port="in[0:2]"/>
<port name="out" physical_mode_port="lut3_out[0:0]"/> <port name="out" physical_mode_port="lut3_out[0:0]"/>
</pb_type> </pb_type>
<pb_type name="clb.fle[shared_lut4_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4"> <!-- BLE4 LUT uses the frac_LUT4 of physical mode:
Index in CLB of BLE4 LUT -> Index in CLB of physical mode LUT
LUT[0] -> LUT[0]
LUT[1] -> LUT[1]
LUT[2] -> LUT[2]
...
-->
<pb_type name="clb.fle[shared_lut3_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 --> <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/> <port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/> <port name="out" physical_mode_port="lut4_out"/>
</pb_type> </pb_type>
<pb_type name="clb.fle[shared_lut3_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <!-- BLE3 FF uses the first FF of physical mode:
Index in CLB of BLE3 FF -> Index in CLB of physical mode FFs
FF[0] -> FF[0]
FF[1] -> FF[2]
FF[2] -> FF[4]
...
-->
<pb_type name="clb.fle[shared_lut3_lut4].ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- BLE3 FF uses the second FF of physical mode:
Index in CLB of BLE3 FF -> Index in CLB of physical mode FFs
FF[0] -> FF[1]
FF[1] -> FF[3]
FF[2] -> FF[5]
...
-->
<pb_type name="clb.fle[shared_lut3_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations> </pb_type_annotations>
</openfpga_architecture> </openfpga_architecture>

67
openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml
View File

@ -301,10 +301,10 @@
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- 3-LUT + LUT4 with shared inputs mode definition begin --> <!-- 3-LUT + LUT4 with shared inputs mode definition begin -->
<mode name="shared_lut4_lut3"> <mode name="shared_lut3_lut4">
<pb_type name="ble4" num_pb="1"> <pb_type name="ble3" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT3 --> <!-- Define LUT3 -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
@ -317,6 +317,32 @@
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux>
</interconnect>
</pb_type>
<pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT4 --> <!-- Define LUT4 -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
@ -330,7 +356,7 @@
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
@ -338,33 +364,26 @@
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble4.in[3:0]" output="lut4[0:0].in[3:0]"/>
<direct name="direct2" input="ble4.in[3:0]" output="lut4[0:0].in[3:0]"/> <direct name="direct2" input="lut4[0:0].out" output="ff[0:0].D">
<direct name="direct3" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble4" in_port="lut4[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct4" input="lut4[0:0].out" output="ff[1:1].D"> <direct name="direct3" input="ble4.clk" output="ff[0:0].clk"/>
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <mux name="mux1" input="ff[0:0].Q lut4.out[0:0]" output="ble4.out[0:0]">
<pack_pattern name="ble3" in_port="lut4[0:0].out" out_port="ff[1:1].D"/>
</direct>
<direct name="direct5" input="ble4.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble4.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble4.out[0:0]"/> <delay_constant max="25e-12" in_port="lut4.out[0:0]" out_port="ble4.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble4.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble4.out[0:0]"/>
</mux> </mux>
<mux name="mux2" input="ff[1:1].Q lut4.out[0:0]" output="ble4.out[1:1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out[0:0]" out_port="ble4.out[1:1]"/>
<delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="ble4.out[1:1]"/>
</mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[3:0]" output="ble4.in"/> <direct name="direct1" input="fle.in[2:0]" output="ble3.in"/>
<direct name="direct2" input="ble4.out" output="fle.out"/> <direct name="direct2" input="fle.in[3:0]" output="ble4.in"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="ble3.out" output="fle.out[0:0]"/>
<direct name="direct4" input="ble4.out" output="fle.out[1:1]"/>
<direct name="direct5" input="fle.clk" output="ble3.clk"/>
<direct name="direct6" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 3-LUT mode definition end --> <!-- Dual 3-LUT mode definition end -->