From a52ef95ef04d20d32fbf1c926f88359fd8bf2b23 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 9 Oct 2018 14:58:47 -0600 Subject: [PATCH] Trying to resize the images in XML --- examples/Examples_README.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/examples/Examples_README.md b/examples/Examples_README.md index 1c11126bb..71e6d7247 100644 --- a/examples/Examples_README.md +++ b/examples/Examples_README.md @@ -6,7 +6,7 @@ The goal of this example is just to make a first step into the software. The .bl The .xml is currently on which means that the size depends on the .blif. Since the .blif is almost empty, only 1 CLB will be generated. -![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png "Example_1_FPGA") +![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png "Example_1_FPGA"){:height="80%" width="80%"} Schematic of the FPGA generated during example_1. The CLB integrates a 4-inputs LUT, a FF and a MUX. @@ -45,14 +45,14 @@ Everything won't be explained in detail but few important structures (some commo ``` - +--- ## Example_2 Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout. In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry. -There is a feedbeck-loop from the output of the slices to the input MUXs +There is a feedback-loop from the output of the slices to the input MUXs -![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB") +![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB"){:height="80%" width="80%"} Schematic showing the CLB generated in this example. @@ -69,6 +69,8 @@ Schematic showing the CLB generated in this example. ``` + +![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_3x3.png "Example_3_FPGA"){:height="80%" width="80%"}