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reorganize the Travis regression test, temporarily shadow s298

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tangxifan 2019-11-01 11:09:35 -06:00
parent 49bfb3223c
commit a49010d2d3
1 changed files with 16 additions and 1 deletions
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17
.travis/script.sh
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@ -18,5 +18,20 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
python3 openfpga_flow/scripts/run_fpga_task.py single_mode s298 blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode
#python3 openfpga_flow/scripts/run_fpga_task.py s298
echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4
echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
echo -e "Testing tileable architectures";
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing explicit_verilog
echo -e "Testing Verilog generation with explicit port mapping ";
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
end_section "OpenFPGA.TaskTun"