From a4893e27cfd6386a4021f0f0fd3828306463ea17 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 11 Apr 2021 17:26:27 -0600 Subject: [PATCH] [Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification --- .../generate_fabric_example_script.openfpga | 2 +- .../generate_testbench_example_script.openfpga | 2 +- .../basic_tests/generate_fabric/config/task.conf | 4 ++++ .../generate_testbench/config/task.conf | 14 +++++++++----- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga index fcbf6e144..467cac0c3 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga @@ -26,7 +26,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose +write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index b88e5370a..197c350bd 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -51,7 +51,7 @@ write_fabric_bitstream --file fabric_bitstream --format xml # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf index db41b7f5a..958c8b9ec 100644 --- a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf @@ -20,6 +20,10 @@ arch_variable_file=${PATH:TASK_DIR}/design_variables.yml openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +# Use a absolute path for the Verilog netlists to be generated +# This is designed to allow the test case 'basic_tests/generate_testbench' +# to use the Verilog netlists along with testbenches in HDL simulation +openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf index 42d3c5733..db8399fbb 100644 --- a/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf @@ -12,23 +12,27 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif +timeout_each_job = 1*60 +fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +# Here, we use a fabric netlist generated by another task +# to show case the correctness of testbench generator +# Caution: You MUST run the task 'basic_tests/generate_fabric' +# before this task!!! +openfpga_fabric_verilog_netlist=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fabric_netlists.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test=