[arch] format
This commit is contained in:
tangxifan
parent
02a5057449
commit
a3f2ae3c33
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@ -185,13 +185,10 @@
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<!-- fpga_input pb_type annoptation -->
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<pb_type name="fpga_input" physical_mode_name="physical"/>
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<pb_type name="fpga_output" physical_mode_name="physical"/>
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<pb_type name="fpga_input[physical].iopad" circuit_model_name="GPIN"/>
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<pb_type name="fpga_output[physical].iopad" circuit_model_name="GPOUT"/>
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<pb_type name="fpga_input[inpad].inpad" physical_pb_type_name="fpga_input[physical].iopad"/>
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<pb_type name="fpga_output[outpad].outpad" physical_pb_type_name="fpga_output[physical].iopad"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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@ -15,216 +15,208 @@
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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-->
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<architecture>
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<models>
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<!-- A virtual model for I/O to be used in the physical mode of io block -->
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<model name="io_inpad">
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<output_ports>
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<port name="inpad"/>
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</output_ports>
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</model>
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<model name="io_outpad">
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<input_ports>
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<port name="outpad"/>
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</input_ports>
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</model>
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</models>
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<tiles>
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<tile name="hybrid_io_tile" area="0">
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<sub_tile name="fpga_input" capacity="8">
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<equivalent_sites>
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<site pb_type="fpga_input"/>
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</equivalent_sites>
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<output name="inpad" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left"> fpga_input.inpad</loc>
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<loc side="top"> fpga_input.inpad</loc>
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<loc side="right"> fpga_input.inpad</loc>
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<loc side="bottom"> fpga_input.inpad</loc>
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</pinlocations>
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</sub_tile>
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<sub_tile name="fpga_output" capacity="8">
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<equivalent_sites>
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<site pb_type="fpga_output"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left"> fpga_output.outpad</loc>
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<loc side="top"> fpga_output.outpad</loc>
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<loc side="right"> fpga_output.outpad</loc>
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<loc side="bottom"> fpga_output.outpad</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="clb" area="53894">
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<sub_tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="10" equivalent="full"/>
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<output name="O" num_pins="4" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="spread"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout tileable="true">
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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<fixed_layout name="2x2" width="10" height="10">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="hybrid_io_tile" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<area grid_logic_tile_area="0"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<pb_type name="fpga_input">
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<output name="inpad" num_pins="1"/>
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<mode name="physical" disable_packing="true">
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<pb_type name="iopad" blif_model=".subckt io_inpad" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="iopad.inpad" output="fpga_input.inpad"/>
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</interconnect>
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</mode>
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="fpga_input.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="fpga_input.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<models>
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<!-- A virtual model for I/O to be used in the physical mode of io block -->
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<model name="io_inpad">
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<output_ports>
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<port name="inpad"/>
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</output_ports>
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</model>
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<model name="io_outpad">
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<input_ports>
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<port name="outpad"/>
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</input_ports>
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</model>
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</models>
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<tiles>
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<tile name="hybrid_io_tile" area="0">
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<sub_tile name="fpga_input" capacity="4">
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<equivalent_sites>
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<site pb_type="fpga_input"/>
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</equivalent_sites>
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<output name="inpad" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left"> fpga_input.inpad</loc>
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<loc side="top"> fpga_input.inpad</loc>
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<loc side="right"> fpga_input.inpad</loc>
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<loc side="bottom"> fpga_input.inpad</loc>
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</pinlocations>
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</sub_tile>
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<sub_tile name="fpga_output" capacity="2">
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<equivalent_sites>
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<site pb_type="fpga_output"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left"> fpga_output.outpad</loc>
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<loc side="top"> fpga_output.outpad</loc>
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<loc side="right"> fpga_output.outpad</loc>
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<loc side="bottom"> fpga_output.outpad</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="clb" area="53894">
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<sub_tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="10" equivalent="full"/>
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<output name="O" num_pins="4" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="spread"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout tileable="true">
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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<fixed_layout name="2x2" width="10" height="10">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="hybrid_io_tile" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<area grid_logic_tile_area="0"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<pb_type name="fpga_input">
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<output name="inpad" num_pins="1"/>
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<mode name="physical" disable_packing="true">
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<pb_type name="iopad" blif_model=".subckt io_inpad" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<pb_type name="fpga_output">
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<input name="outpad" num_pins="1"/>
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<mode name="physical" disable_packing="true">
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<pb_type name="iopad" blif_model=".subckt io_outpad" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="fpga_output.outpad" output="iopad.outpad"/>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="fpga_output.outpad" output="outpad.outpad"/>
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</interconnect>
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</mode>
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<interconnect>
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<direct name="inpad" input="iopad.inpad" output="fpga_input.inpad"/>
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</interconnect>
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</mode>
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<pb_type name="clb">
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<input name="I" num_pins="10" equivalent="full"/>
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<output name="O" num_pins="4" equivalent="none"/>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="fpga_input.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="fpga_input.inpad"/>
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</direct>
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</interconnect>
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</mode>
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</pb_type>
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<pb_type name="fpga_output">
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<input name="outpad" num_pins="1"/>
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<mode name="physical" disable_packing="true">
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<pb_type name="iopad" blif_model=".subckt io_outpad" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="fpga_output.outpad" output="iopad.outpad"/>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="fpga_output.outpad" output="outpad.outpad"/>
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</interconnect>
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</mode>
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</pb_type>
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<pb_type name="clb">
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<input name="I" num_pins="10" equivalent="full"/>
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<output name="O" num_pins="4" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="fle" num_pb="4">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- 4-LUT mode definition begin -->
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<mode name="n1_lut4">
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<!-- Define 4-LUT mode -->
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<pb_type name="ble4" num_pb="1">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="fle" num_pb="4">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- 4-LUT mode definition begin -->
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<mode name="n1_lut4">
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<!-- Define 4-LUT mode -->
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<pb_type name="ble4" num_pb="1">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define LUT -->
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<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="4" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
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<!-- Define LUT -->
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<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="4" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
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261e-12
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261e-12
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261e-12
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261e-12
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
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<direct name="direct2" input="lut4.out" output="ff.D">
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<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
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<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
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</direct>
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<direct name="direct3" input="ble4.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="ble4.in"/>
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<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
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<direct name="direct3" input="fle.clk" output="ble4.clk"/>
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</interconnect>
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</mode>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
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<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
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<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
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</complete>
|
||||
|
||||
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
</complexblocklist>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
||||
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
||||
</complete>
|
||||
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
|
|
|
|||
Loading…
Reference in New Issue