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OpenFPGA
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[arch] format

This commit is contained in:
tangxifan 2023-05-03 15:23:47 +08:00
parent 02a5057449
commit a3f2ae3c33
2 changed files with 193 additions and 204 deletions
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3
openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_openfpga.xml
View File

@ -185,13 +185,10 @@
<!-- fpga_input pb_type annoptation -->
<pb_type name="fpga_input" physical_mode_name="physical"/>
<pb_type name="fpga_output" physical_mode_name="physical"/>
<pb_type name="fpga_input[physical].iopad" circuit_model_name="GPIN"/>
<pb_type name="fpga_output[physical].iopad" circuit_model_name="GPOUT"/>
<pb_type name="fpga_input[inpad].inpad" physical_pb_type_name="fpga_input[physical].iopad"/>
<pb_type name="fpga_output[outpad].outpad" physical_pb_type_name="fpga_output[physical].iopad"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->

12
openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_40nm.xml
View File

@ -30,7 +30,7 @@
</models>
<tiles>
<tile name="hybrid_io_tile" area="0">
<sub_tile name="fpga_input" capacity="8">
<sub_tile name="fpga_input" capacity="4">
<equivalent_sites>
<site pb_type="fpga_input"/>
</equivalent_sites>
@ -43,7 +43,7 @@
<loc side="bottom"> fpga_input.inpad</loc>
</pinlocations>
</sub_tile>
<sub_tile name="fpga_output" capacity="8">
<sub_tile name="fpga_output" capacity="2">
<equivalent_sites>
<site pb_type="fpga_output"/>
</equivalent_sites>
@ -101,7 +101,6 @@
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
@ -113,7 +112,6 @@
</segment>
</segmentlist>
<complexblocklist>
<pb_type name="fpga_input">
<output name="inpad" num_pins="1"/>
<mode name="physical" disable_packing="true">
@ -135,10 +133,8 @@
</interconnect>
</mode>
</pb_type>
<pb_type name="fpga_output">
<input name="outpad" num_pins="1"/>
<mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io_outpad" num_pb="1">
<input name="outpad" num_pins="1"/>
@ -147,7 +143,6 @@
<direct name="outpad" input="fpga_output.outpad" output="iopad.outpad"/>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
@ -156,9 +151,7 @@
<direct name="outpad" input="fpga_output.outpad" output="outpad.outpad"/>
</interconnect>
</mode>
</pb_type>
<pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/>
@ -222,7 +215,6 @@
</complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete>
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect>
</pb_type>