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Preserve escaped names

This commit is contained in:
alaindargelas 2024-03-04 09:27:12 -08:00
parent deed17d736
commit a3d627b21f
1 changed files with 168 additions and 166 deletions
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26
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
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@ -84,8 +84,8 @@ void print_verilog_testbench_fpga_instance(
module_manager.module_port(top_module, module_port_id);
/* Bypass dummy port: the port does not exist at core module */
if (io_name_map.fpga_top_port_is_dummy(module_port)) {
ModulePortId core_module_port =
module_manager.find_module_port(core_module, module_port.get_name());
ModulePortId core_module_port = module_manager.find_module_port(
core_module, module_port.get_name());
if (!module_manager.valid_module_port_id(core_module,
core_module_port)) {
/* Print the wire for the dummy port */
@ -132,7 +132,8 @@ void print_verilog_testbench_benchmark_instance(
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix, const std::string& output_port_postfix,
const std::string& input_port_postfix,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_port_postfix, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
@ -296,7 +297,8 @@ void print_verilog_testbench_benchmark_instance(
if (0 < pin_counter) {
fp << ", ";
}
std::string escapedName = bus_group.pin_name(pin) + output_port_postfix;
std::string escapedName =
bus_group.pin_name(pin) + output_port_postfix;
escapedName = escapeNames(escapedName);
fp << escapedName;
pin_counter++;
@ -653,8 +655,8 @@ void print_verilog_testbench_check(
print_verilog_comment(
fp, std::string("----- Begin checking output vectors -------"));
std::vector<BasicPort> clock_ports =
generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(
clock_port_names, default_clock_name);
print_verilog_comment(fp,
std::string("----- Skip the first falling edge of "
@ -881,8 +883,8 @@ void print_verilog_testbench_random_stimuli(
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= 1'b0;"
<< std::endl;
fp << "\t\t" << escapeNames(block_name + input_port_postfix)
<< " <= 1'b0;" << std::endl;
}
}
@ -965,8 +967,8 @@ void print_verilog_testbench_random_stimuli(
/* TODO: find the clock inputs will be initialized later */
if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= $random;"
<< std::endl;
fp << "\t\t" << escapeNames(block_name + input_port_postfix)
<< " <= $random;" << std::endl;
}
}
@ -990,8 +992,8 @@ void print_verilog_testbench_shared_input_ports(
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_ports, const std::string& shared_input_port_postfix,
const bool& use_reg_port) {
const bool& include_clock_ports,
const std::string& shared_input_port_postfix, const bool& use_reg_port) {
/* Validate the file stream */
valid_file_stream(fp);