From a3c982a83f896061b008865b689c5c5080897e95 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 23 Sep 2020 17:27:16 -0600
Subject: [PATCH] [Architecture] Patch the openfpga architecture using
 active-low configurable latch

---
 .../openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml
index 27df66764..efefbf581 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml
@@ -146,7 +146,7 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_neg_rst.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>