diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_template.xml b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_template.xml new file mode 100644 index 000000000..6c5f95307 --- /dev/null +++ b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_template.xml @@ -0,0 +1,1010 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 10e-12 10e-12 + + + 10e-12 10e-12 10e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/vpr7_x2p/vpr/Circuits/test_modes.act b/vpr7_x2p/vpr/Circuits/test_modes.act new file mode 100644 index 000000000..a58956a8e --- /dev/null +++ b/vpr7_x2p/vpr/Circuits/test_modes.act @@ -0,0 +1,67 @@ +cint01 0.485400 0.188600 +n01 0.489000 0.213200 +cint02 0.502400 0.203200 +n02 0.509200 0.195200 +cint03 0.507200 0.192200 +n03 0.502400 0.201600 +cint04 0.463200 0.199400 +n04 0.522000 0.191000 +n05 0.486800 0.204800 +reg0 0.463000 0.195400 +reg1 0.487400 0.196600 +reg2 0.506200 0.195000 +reg3 0.492200 0.208200 +reg4 0.507200 0.204800 +reg5 0.500400 0.200600 +reg6 0.500800 0.203400 +reg7 0.509600 0.198800 +reg8 0.492200 0.188000 +reg9 0.504800 0.204400 +reg10 0.507600 0.203200 +reg11 0.494200 0.203600 +clk 0.534600 0.203800 +a_0 0.478200 0.203800 +a_1 0.514800 0.208600 +a_2 0.505800 0.204600 +a_3 0.500000 0.195200 +b_0 0.530800 0.192800 +b_1 0.495800 0.195400 +b_2 0.496600 0.201200 +b_3 0.492000 0.200200 +cin 0.502600 0.202200 +e 0.495200 0.201000 +f 0.504000 0.203400 +g 0.498200 0.202000 +reg_a_0 0.478200 0.203800 +reg_a_1 0.514800 0.208600 +reg_a_2 0.505800 0.204600 +reg_a_3 0.500000 0.195200 +reg_b_0 0.530800 0.192800 +reg_b_1 0.495800 0.195400 +reg_b_2 0.496600 0.201200 +reg_b_3 0.492000 0.200200 +reg_cin 0.502600 0.202200 +sum_0 0.489000 0.213200 +sum_1 0.509200 0.195200 +sum_2 0.502400 0.201600 +sum_3 0.522000 0.191000 +cout 0.486800 0.204800 +ref0 0.000000 0.000000 +n57 0.478200 0.097457 +n62 0.514800 0.107387 +n67 0.505800 0.103487 +n72 0.500000 0.097600 +n77 0.530800 0.102338 +n82 0.495800 0.096879 +n87 0.496600 0.099916 +n92 0.492000 0.098498 +n97 0.502600 0.101626 +d0 0.617800 0.046719 +x 0.492200 0.102476 +y 0.509600 0.101308 +z 0.494200 0.100619 +n102 0.489000 0.104255 +n106 0.509200 0.099396 +n110 0.502400 0.101284 +n114 0.522000 0.099702 +n118 0.486800 0.099697 diff --git a/vpr7_x2p/vpr/Circuits/test_modes.blif b/vpr7_x2p/vpr/Circuits/test_modes.blif new file mode 100644 index 000000000..d63bca69d --- /dev/null +++ b/vpr7_x2p/vpr/Circuits/test_modes.blif @@ -0,0 +1,93 @@ +# Benchmark "test" written by ABC on Tue Apr 30 17:17:10 2019 +.model test_modes +.inputs clk a_0 a_1 a_2 a_3 b_0 b_1 b_2 b_3 cin e f g +.outputs sum_0 sum_1 sum_2 sum_3 cout x y z + +.latch n57 reg_a_0 re clk 0 +.latch n62 reg_a_1 re clk 0 +.latch n67 reg_a_2 re clk 0 +.latch n72 reg_a_3 re clk 0 +.latch n77 reg_b_0 re clk 0 +.latch n82 reg_b_1 re clk 0 +.latch n87 reg_b_2 re clk 0 +.latch n92 reg_b_3 re clk 0 +.latch n97 reg_cin re clk 0 +.latch n102 sum_0 re clk 0 +.latch n106 sum_1 re clk 0 +.latch n110 sum_2 re clk 0 +.latch n114 sum_3 re clk 0 +.latch n118 cout re clk 0 + + +.subckt adder a=reg_a_0 b=reg_b_0 cin=reg_cin cout=cint01 sumout=n01 +.subckt adder a=reg_a_1 b=reg_b_1 cin=cint01 cout=cint02 sumout=n02 +.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03 +.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04 +.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05 +.subckt shift D=d0 clk=clk Q=reg0 +.subckt shift D=reg0 clk=clk Q=reg1 +.subckt shift D=reg1 clk=clk Q=reg2 +.subckt shift D=reg2 clk=clk Q=reg3 +.subckt shift D=reg3 clk=clk Q=reg4 +.subckt shift D=reg4 clk=clk Q=reg5 +.subckt shift D=reg5 clk=clk Q=reg6 +.subckt shift D=reg6 clk=clk Q=reg7 +.subckt shift D=reg7 clk=clk Q=reg8 +.subckt shift D=reg8 clk=clk Q=reg9 +.subckt shift D=reg9 clk=clk Q=reg10 +.subckt shift D=reg10 clk=clk Q=reg11 + +.names ref0 + 0 +.names a_0 n57 +1 1 +.names a_1 n62 +1 1 +.names a_2 n67 +1 1 +.names a_3 n72 +1 1 +.names b_0 n77 +1 1 +.names b_1 n82 +1 1 +.names b_2 n87 +1 1 +.names b_3 n92 +1 1 +.names cin n97 +1 1 +.names e f g d0 +1-1 1 +-0- 1 +.names reg3 x +1 1 +.names reg7 y +1 1 +.names reg11 z +1 1 +.names n01 n102 +1 1 +.names n02 n106 +1 1 +.names n03 n110 +1 1 +.names n04 n114 +1 1 +.names n05 n118 +1 1 +.end + + +.model adder +.inputs a b cin +.outputs cout sumout +.blackbox +.end + + +.model shift +.inputs D clk +.outputs Q +.blackbox +.end diff --git a/vpr7_x2p/vpr/Circuits/test_modes.v b/vpr7_x2p/vpr/Circuits/test_modes.v new file mode 100644 index 000000000..8090d2903 --- /dev/null +++ b/vpr7_x2p/vpr/Circuits/test_modes.v @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////// +// // +// Benchmark using all modes of k8 architecture // +// // +//////////////////////////////////////////////////////// + +`timescale 1 ns/ 1 ps + +module test_modes( + clk, + a_0, + a_1, + a_2, + a_3, + b_0, + b_1, + b_2, + b_3, + cin, + e, + f, + g, + sum_0, + sum_1, + sum_2, + sum_3, + cout, + x, + y, + z ); + + input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g; + output reg sum_0, sum_1, sum_2, sum_3, cout; + output wire x, y, z; + + wire d0; + wire [4:0] n0; + wire [3:0] a, b; + reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin; + + assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0}; + assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0}; + assign d0 = (e && g) || !f; + assign n0 = a + b + reg_cin; + assign x = reg3; + assign y = reg7; + assign z = reg11; + + always @(posedge clk) begin + reg0 <= d0; + reg1 <= reg0; + reg2 <= reg1; + reg3 <= reg2; + reg4 <= reg3; + reg5 <= reg4; + reg6 <= reg5; + reg7 <= reg6; + reg8 <= reg7; + reg9 <= reg8; + reg10 <= reg9; + reg11 <= reg10; + reg_a_0 <= a_0; + reg_a_1 <= a_1; + reg_a_2 <= a_2; + reg_a_3 <= a_3; + reg_b_0 <= b_0; + reg_b_1 <= b_1; + reg_b_2 <= b_2; + reg_b_3 <= b_3; + reg_cin <= cin; + sum_0 <= n0[0]; + sum_1 <= n0[1]; + sum_2 <= n0[2]; + sum_3 <= n0[3]; + cout <= n0[4]; + end + +endmodule diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c index 9d6a302a5..cac372cfa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c @@ -43,6 +43,7 @@ /* Local variables */ static char* autocheck_testbench_reference_output_postfix = "_benchmark"; static char* autocheck_testbench_verification_output_postfix = "_verification"; +static char* error_counter = "nb_error"; /* Local Subroutines declaration */ @@ -203,6 +204,10 @@ void dump_verilog_top_auto_testbench_ports(FILE* fp, } } +// Instantiate an integer to count the number of error and determine if the simulation succeed or failed + fprintf(fp, "\n//----- Error counter \n"); + fprintf(fp, " integer %s = 0;\n\n", error_counter); + return; } @@ -277,9 +282,15 @@ void dump_verilog_timeout_and_vcd(FILE * fp, modelsim_autocheck_testbench_module_postfix); fprintf(fp, " end\n\n"); fprintf(fp, " initial begin\n"); + fprintf(fp, " $timeformat(-9, 2, \"ns\", 20);\n"); fprintf(fp, " $display(\"Simulation start\");\n"); fprintf(fp, " #%i // Can be changed by the user for his need\n", simulation_time); - fprintf(fp, " $display(\"Simulation End: Time's up\");\n"); + fprintf(fp, " if(%s == 0) begin\n", error_counter); + fprintf(fp, " $display(\"Simulation Succeed\");\n"); + fprintf(fp, " end else begin\n"); + fprintf(fp, " $display(\"Simulation Failed with %s error(s)\", %s);\n", "%d", error_counter); + fprintf(fp, " end\n"); + fprintf(fp, " $finish;\n"); fprintf(fp, " end\n"); fprintf(fp, "`endif\n\n"); return; @@ -321,10 +332,10 @@ void dump_verilog_top_auto_testbench_check(FILE* fp){ fprintf(fp, " if(%s%s) begin\n", logical_block[iblock].name, autocheck_testbench_verification_output_postfix); - fprintf(fp, " $display(\"Mismatch on %s%s\");\n", + fprintf(fp, " %s = %s + 1;\n", error_counter, error_counter); + fprintf(fp, " $display(\"Mismatch on %s%s at time = %s\", $realtime);\n", logical_block[iblock].name, - autocheck_testbench_verification_output_postfix); - fprintf(fp, " $finish;\n"); + autocheck_testbench_verification_output_postfix, "%t"); fprintf(fp, " end\n"); fprintf(fp, " end\n\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c index 53983ce11..88103cc8c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c @@ -46,6 +46,7 @@ static char* gfpga_postfix = "_gfpga"; static char* bench_postfix = "_bench"; static char* flag_postfix = "_flag"; static char* def_clk_name = "clk"; +static char* error_counter = "nb_error"; static char* clock_input_name = NULL; /* Local Subroutines declaration */ @@ -126,6 +127,9 @@ void dump_verilog_top_random_testbench_ports(FILE* fp, } } } fprintf(fp, "`endif\n"); +// Instantiate an integer to count the number of error and determine if the simulation succeed or failed + fprintf(fp, "\n//----- Error counter \n"); + fprintf(fp, " integer %s = 0;\n\n", error_counter); return; } @@ -172,7 +176,7 @@ int get_simulation_time(int num_prog_clock_cycles, int total_time_period = 0; /* Take into account the prog_reset and reset cycles */ - total_time_period = ((num_prog_clock_cycles + 2) * prog_clock_period + (2 * num_op_clock_cycles * op_clock_period)) * 1000000000; // * 1000000000 is to change the unit to ns rather than second + total_time_period = (100 * (2 * num_op_clock_cycles * op_clock_period)) * 1000000000; // * 1000000000 is to change the unit to ns rather than second return total_time_period; } @@ -197,9 +201,15 @@ void dump_verilog_timeout_and_vcd(FILE * fp, formal_random_top_tb_postfix); fprintf(fp, " end\n\n"); fprintf(fp, " initial begin\n"); + fprintf(fp, " $timeformat(-9, 2, \"ns\", 20);\n"); fprintf(fp, " $display(\"Simulation start\");\n"); fprintf(fp, " #%i // Can be changed by the user for his need\n", simulation_time); - fprintf(fp, " $display(\"Simulation End: Time's up\");\n"); + fprintf(fp, " if(%s == 0) begin\n", error_counter); + fprintf(fp, " $display(\"Simulation Succeed\");\n"); + fprintf(fp, " end else begin\n"); + fprintf(fp, " $display(\"Simulation Failed with %s error(s)\", %s);\n", "%d", error_counter); + fprintf(fp, " end\n"); + fprintf(fp, " $finish;\n"); fprintf(fp, " end\n"); fprintf(fp, "`endif\n\n"); return; @@ -238,9 +248,9 @@ void dump_verilog_top_random_testbench_check(FILE* fp){ flag_postfix); fprintf(fp, " if(%s%s) begin\n", logical_block[iblock].name, flag_postfix); - fprintf(fp, " $display(\"Mismatch on %s%s\");\n", logical_block[iblock].name, - gfpga_postfix); - fprintf(fp, " $finish;\n"); + fprintf(fp, " %s = %s + 1;\n", error_counter, error_counter); + fprintf(fp, " $display(\"Mismatch on %s%s at time = %s\", $realtime);\n", logical_block[iblock].name, + gfpga_postfix, "%t"); fprintf(fp, " end\n"); fprintf(fp, " end\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 5db4558c6..92d15d0fc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -102,8 +102,8 @@ void dump_verilog_submodule_signal_init(FILE* fp, fprintf(fp, "\n`ifdef %s\n", verilog_signal_init_preproc_flag); fprintf(fp, " //------ BEGIN driver initialization -----\n"); fprintf(fp, "initial begin\n"); - fprintf(fp, "`ifdef %s\n #0.001\n`endif\n", - icarus_simulator_flag); +// fprintf(fp, "`ifdef %s\n #0.001\n`endif\n", // Commented, looks no longer needed +// icarus_simulator_flag); for (iport = 0; iport < num_input_port; iport++) { fprintf(fp, " $deposit(%s, $random);\n", input_port[iport]->lib_name); diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff.v b/vpr7_x2p/vpr/VerilogNetlists/ff.v new file mode 100644 index 000000000..8a2da5988 --- /dev/null +++ b/vpr7_x2p/vpr/VerilogNetlists/ff.v @@ -0,0 +1,114 @@ +//----------------------------------------------------- +// Design Name : static_dff +// File Name : ff.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +//------ Include defines: preproc flags ----- +`include "/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/vpr7_x2p/vpr/s298_prevpr_Verilog/SRC/fpga_defines.v" +module static_dff ( +/* Global ports go first */ +input set, // set input +input reset, // Reset input +input clk, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or posedge reset or posedge set) +if (reset) begin + q_reg <= 1'b0; +end else if (set) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +assign Q = q_reg; + +endmodule //End Of Module static_dff + +//----------------------------------------------------- +// Design Name : scan_chain_dff +// File Name : ff.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +module sc_dff ( +/* Global ports go first */ +input set, // set input +input reset, // Reset input +input clk, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q, // Q output +output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or posedge reset or posedge set) +if (reset) begin + q_reg <= 1'b0; +end else if (set) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~Q; + +endmodule //End Of Module static_dff + +//----------------------------------------------------- +// Design Name : scan_chain_dff compact +// File Name : ff.v +// Function : Scan-chain D flip-flop without reset and set //Modified to fit Edouards architecture +// Coder : Xifan TANG +//----------------------------------------------------- +module sc_dff_compact ( +/* Global ports go first */ +input reset, // Reset input +//input set, // set input +input clk, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q, // Q output +output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or posedge reset /*or posedge set*/) +if (reset) begin + q_reg <= 1'b0; +//end else if (set) begin +// q_reg <= 1'b1; +end else begin + q_reg <= D; +end +/* +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~Q; +*/ + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule //End Of Module static_dff diff --git a/vpr7_x2p/vpr/VerilogNetlists/sram.v b/vpr7_x2p/vpr/VerilogNetlists/sram.v new file mode 100644 index 000000000..536c1012a --- /dev/null +++ b/vpr7_x2p/vpr/VerilogNetlists/sram.v @@ -0,0 +1,97 @@ +//------ Module: sram6T_blwl -----// +//------ Verilog file: sram.v -----// +//------ Author: Xifan TANG -----// +module sram6T_blwl( +//input read, +//input nequalize, +input din, // Data input +output dout, // Data output +output doutb, // Data output +input bl, // Bit line control signal +input wl, // Word line control signal +input blb // Inverted Bit line control signal +); + //----- local variable need to be registered + reg a; + + //----- when wl is enabled, we can read in data from bl + always @(bl, wl) + begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + if ((1'b1 == bl)&&(1'b1 == wl)) begin + a <= 1'b1; + end + //----- case 2: bl = 0, wl = 1, a -> 0 + if ((1'b0 == bl)&&(1'b1 == wl)) begin + a <= 1'b0; + end + end + + // dout is short-wired to din + assign dout = a; + //---- doutb is always opposite to dout + assign doutb = ~dout; +`ifdef ENABLE_SIGNAL_INITIALIZATION + initial begin + $deposit(a, $random); + end +`endif +endmodule + +module sram6T_rram( +input read, +input nequalize, +input din, // Data input +output dout, // Data output +output doutb, // Data output +// !!! Port bit position should start from LSB to MSB +// Follow this convention for BL/WLs in each module! +input [0:2] bl, // Bit line control signal +input [0:2] wl// Word line control signal +); + //----- local variable need to be registered + //----- Modeling two RRAMs + reg r0, r1; + + always @(bl[0], wl[2]) + begin + //----- Cases to program r0 + //----- case 1: bl[0] = 1, wl[2] = 1, r0 -> 0 + if ((1'b1 == bl[0])&&(1'b1 == wl[2])) begin + r0 <= 0; + end + end + + always @(bl[2], wl[0]) + begin + //----- case 2: bl[2] = 1, wl[0] = 1, r0 -> 1 + if ((1'b1 == bl[2])&&(1'b1 == wl[0])) begin + r0 <= 1; + end + end + + always @(bl[1], wl[2]) + begin + //----- Cases to program r1 + //----- case 1: bl[1] = 1, wl[2] = 1, r0 -> 0 + if ((1'b1 == bl[1])&&(1'b1 == wl[2])) begin + r1 <= 0; + end + end + + always @( bl[2], wl[1]) + begin + //----- case 2: bl[2] = 1, wl[1] = 1, r0 -> 1 + if ((1'b1 == bl[2])&&(1'b1 == wl[1])) begin + r1 <= 1; + end + end + + // dout is r0 AND r1 + assign dout = r0 | (~r1); + + //---- doutb is always opposite to dout + assign doutb = ~dout; + +endmodule