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[Test] Deploy test case to CI

This commit is contained in:
tangxifan 2020-11-02 12:29:20 -07:00
parent bc00dee858
commit a346c529aa
1 changed files with 3 additions and 0 deletions
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.travis/fpga_verilog_reg_test.sh
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@ -43,6 +43,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity
echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs
echo -e "Testing Verilog generation with adder chain across an FPGA";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs