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BugFix : Relative path for refrence benchmark fixed

This commit is contained in:
ganeshgore 2020-04-25 20:16:17 -06:00
parent 9d1b3d6865
commit a3103f6afe
2 changed files with 4 additions and 4 deletions
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6
openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
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@ -40,8 +40,8 @@ build_fabric_bitstream --verbose
write_fabric_verilog --file ./SRC \ write_fabric_verilog --file ./SRC \
--explicit_port_mapping \ --explicit_port_mapping \
--include_timing \ --include_timing \
--include_signal_init --include_signal_init
#--support_icarus_simulator #--support_icarus_simulator
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists
@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC \
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini
# Write the SDC files for PnR backend # Write the SDC files for PnR backend
# - Turn on every options here # - Turn on every options here

2
openfpga_flow/scripts/run_modelsim.py
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@ -182,7 +182,7 @@ def create_tcl_script(files):
with open(IncludeFileResolved, "w") as fpw: with open(IncludeFileResolved, "w") as fpw:
with open(IncludeFile, "r") as fp: with open(IncludeFile, "r") as fp:
for eachline in fp.readlines(): for eachline in fp.readlines():
eachline = eachline.replace("./SRC", "../../../SRC/") eachline = eachline.replace("\"./", "\"../../../")
fpw.write(eachline) fpw.write(eachline)
# Modify the variables in config file here # Modify the variables in config file here
config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0] config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0]