Add path modification in file changing a keyword into OpenFPGA full path
This commit is contained in:
AurelienUoU
parent
2c6780ab92
commit
a2f6ded2a2
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@ -9,6 +9,13 @@ tb_formal_postfix="_top_formal_verification_random_tb"
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirname="${benchmark}_Verilog"
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log_file="${benchmark}_sim.log"
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log_file="${benchmark}_sim.log"
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cd fpga_flow/scripts
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perl rewrite_path_in_file.pl -i ../arch/template/k6_N10_sram_chain_HC_template.xml
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perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/regression_verilog.sh
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cd -
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# Move to vpr folder
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# Move to vpr folder
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cd vpr7_x2p/vpr
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cd vpr7_x2p/vpr
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@ -17,7 +24,7 @@ rm -f $log_file
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rm -f $compiled_file
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rm -f $compiled_file
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# Start the script -> run the fpga generation -> run the simulation -> check the log file
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# Start the script -> run the fpga generation -> run the simulation -> check the log file
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source .regression_verilog.sh
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source regression_verilog.sh
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iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
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iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
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vvp $compiled_file -j 16 >> $log_file
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vvp $compiled_file -j 16 >> $log_file
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,67 @@
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cint01 0.485400 0.188600
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n01 0.489000 0.213200
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cint02 0.502400 0.203200
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n02 0.509200 0.195200
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cint03 0.507200 0.192200
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n03 0.502400 0.201600
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cint04 0.463200 0.199400
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n04 0.522000 0.191000
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n05 0.486800 0.204800
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reg0 0.463000 0.195400
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reg1 0.487400 0.196600
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reg2 0.506200 0.195000
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reg3 0.492200 0.208200
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reg4 0.507200 0.204800
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reg5 0.500400 0.200600
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reg6 0.500800 0.203400
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reg7 0.509600 0.198800
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reg8 0.492200 0.188000
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reg9 0.504800 0.204400
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reg10 0.507600 0.203200
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reg11 0.494200 0.203600
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clk 0.534600 0.203800
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a_0 0.478200 0.203800
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a_1 0.514800 0.208600
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a_2 0.505800 0.204600
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a_3 0.500000 0.195200
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b_0 0.530800 0.192800
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b_1 0.495800 0.195400
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b_2 0.496600 0.201200
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b_3 0.492000 0.200200
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cin 0.502600 0.202200
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e 0.495200 0.201000
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f 0.504000 0.203400
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g 0.498200 0.202000
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reg_a_0 0.478200 0.203800
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reg_a_1 0.514800 0.208600
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reg_a_2 0.505800 0.204600
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reg_a_3 0.500000 0.195200
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reg_b_0 0.530800 0.192800
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reg_b_1 0.495800 0.195400
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reg_b_2 0.496600 0.201200
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reg_b_3 0.492000 0.200200
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reg_cin 0.502600 0.202200
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sum_0 0.489000 0.213200
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sum_1 0.509200 0.195200
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sum_2 0.502400 0.201600
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sum_3 0.522000 0.191000
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cout 0.486800 0.204800
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ref0 0.000000 0.000000
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n57 0.478200 0.097457
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n62 0.514800 0.107387
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n67 0.505800 0.103487
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n72 0.500000 0.097600
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n77 0.530800 0.102338
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n82 0.495800 0.096879
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n87 0.496600 0.099916
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n92 0.492000 0.098498
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n97 0.502600 0.101626
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d0 0.617800 0.046719
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x 0.492200 0.102476
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y 0.509600 0.101308
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z 0.494200 0.100619
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n102 0.489000 0.104255
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n106 0.509200 0.099396
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n110 0.502400 0.101284
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n114 0.522000 0.099702
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n118 0.486800 0.099697
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@ -0,0 +1,93 @@
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# Benchmark "test" written by ABC on Tue Apr 30 17:17:10 2019
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.model test_modes
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.inputs clk a_0 a_1 a_2 a_3 b_0 b_1 b_2 b_3 cin e f g
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.outputs sum_0 sum_1 sum_2 sum_3 cout x y z
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.latch n57 reg_a_0 re clk 0
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.latch n62 reg_a_1 re clk 0
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.latch n67 reg_a_2 re clk 0
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.latch n72 reg_a_3 re clk 0
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.latch n77 reg_b_0 re clk 0
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.latch n82 reg_b_1 re clk 0
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.latch n87 reg_b_2 re clk 0
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.latch n92 reg_b_3 re clk 0
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.latch n97 reg_cin re clk 0
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.latch n102 sum_0 re clk 0
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.latch n106 sum_1 re clk 0
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.latch n110 sum_2 re clk 0
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.latch n114 sum_3 re clk 0
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.latch n118 cout re clk 0
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.subckt adder a=reg_a_0 b=reg_b_0 cin=reg_cin cout=cint01 sumout=n01
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.subckt adder a=reg_a_1 b=reg_b_1 cin=cint01 cout=cint02 sumout=n02
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.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03
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.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04
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.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05
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.subckt shift D=d0 clk=clk Q=reg0
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.subckt shift D=reg0 clk=clk Q=reg1
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.subckt shift D=reg1 clk=clk Q=reg2
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.subckt shift D=reg2 clk=clk Q=reg3
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.subckt shift D=reg3 clk=clk Q=reg4
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.subckt shift D=reg4 clk=clk Q=reg5
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.subckt shift D=reg5 clk=clk Q=reg6
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.subckt shift D=reg6 clk=clk Q=reg7
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.subckt shift D=reg7 clk=clk Q=reg8
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.subckt shift D=reg8 clk=clk Q=reg9
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.subckt shift D=reg9 clk=clk Q=reg10
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.subckt shift D=reg10 clk=clk Q=reg11
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.names ref0
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0
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.names a_0 n57
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1 1
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.names a_1 n62
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1 1
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.names a_2 n67
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1 1
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.names a_3 n72
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1 1
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.names b_0 n77
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1 1
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.names b_1 n82
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1 1
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.names b_2 n87
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1 1
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.names b_3 n92
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1 1
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.names cin n97
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1 1
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.names e f g d0
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1-1 1
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-0- 1
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.names reg3 x
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1 1
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.names reg7 y
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1 1
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.names reg11 z
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1 1
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.names n01 n102
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1 1
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.names n02 n106
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1 1
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.names n03 n110
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1 1
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.names n04 n114
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1 1
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.names n05 n118
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1 1
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.end
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.model adder
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.inputs a b cin
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.outputs cout sumout
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.blackbox
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.end
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.model shift
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.inputs D clk
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.outputs Q
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.blackbox
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.end
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@ -0,0 +1,172 @@
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----------------------------------- Summary ------------------------------------
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Circuit: /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes
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Architecture: k6_N10_sram_chain_HC_template.xml
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Technology (nm): 45
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Voltage: 0.90
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Temperature: 85
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Critical Path: 5.8141e-09
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Size of FPGA: 2 x 2
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Channel Width: 200
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----------------------------------- Warnings -----------------------------------
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No transistor counter function for BLIF model: .frac_lut6
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No transistor counter function for BLIF model: .subckt adder
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No transistor counter function for BLIF model: .subckt shift
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Attempted to search for a transistor with a capacitance smaller than the smallest in the technology file.
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No dynamic power defined for BLIF model: .subckt adder
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No leakage power defined for BLIF model: .subckt adder
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No dynamic power defined for BLIF model: .frac_lut6
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No leakage power defined for BLIF model: .frac_lut6
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No dynamic power defined for BLIF model: .subckt shift
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No leakage power defined for BLIF model: .subckt shift
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------------------------------- Power Breakdown --------------------------------
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Component Power (W) %-Total %-Dynamic Method
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Total 0.0002701 1 0.7897
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Routing 0.0001289 0.4773 0.7668
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Switch Box 2.212e-05 0.08191 0
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Connection Box 0.0001068 0.3954 0.9256
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Global Wires 0 0 -nan
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PB Types 8.066e-05 0.2986 0.6884
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Primitives 4.913e-05 0.1819 0.8837
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Interc Structures 8.866e-06 0.03283 0.5489
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Buffers and Wires 2.266e-05 0.08389 0.3197
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Other Estimation Methods 0 0 -nan
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Clock 6.051e-05 0.224 0.9736
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---------------------------- Power Breakdown by PB -----------------------------
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This sections provides a detailed breakdown of power usage by PB (physical
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block). For each PB, the power is listed, which is the sum power of all
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instances of the block. It also indicates its percentage of total power (entire
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FPGA), as well as the percentage of its power that is dynamic (vs. static). It
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also indicates the method used for power estimation.
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The data includes:
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Modes: When a pb contains multiple modes, each mode is listed, with
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its power statistics.
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Bufs/Wires: Power of all local buffers and local wire switching
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(transistor-level estimation only).
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Interc: Power of local interconnect multiplexers (transistor-
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level estimation only)
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Description of Estimation Methods:
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Transistor Auto-Size: Transistor-level power estimation. Local buffers and
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wire lengths are automatically sized. This is the default estimation
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method.
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Transistor Specify-Size: Transistor-level power estimation. Local buffers
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and wire lengths are only inserted where specified by the user in the
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architecture file.
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Pin-Toggle: Dynamic power is calculated using enery-per-toggle of the PB
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input pins. Static power is absolute.
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C-Internal: Dynamic power is calculated using an internal equivalent
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capacitance for PB type. Static power is absolute.
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Absolute: Dynamic and static power are absolutes from the architecture file.
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Sum of Children: Power of PB is only the sum of all child PBs; interconnect
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between the PB and its children is ignored.
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Ignore: Power of PB is ignored.
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Component Power (W) %-Total %-Dynamic Method
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io 0 0 -nan Ignore
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clb 8.066e-05 0.2986 0.6884 Transistor Auto-Size
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Bufs/Wires 1.43e-05 0.05294 0.2804
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Interc: 8.462e-06 0.03133 0.542
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crossbar0 3.015e-06 0.01116 0.5188
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crossbar1 3.264e-06 0.01208 0.5568
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crossbar2 1.076e-06 0.003984 0.5484
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crossbar3 8.245e-07 0.003053 0.5364
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crossbar4 0 0 -nan
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crossbar5 0 0 -nan
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clks 0 0 -nan
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carry_in 2.821e-07 0.001045 0.6112
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fle 5.79e-05 0.2144 0.8106 Transistor Auto-Size
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Bufs/Wires 6.769e-06 0.02506 0.3446
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Mode:fle_phy 3.361e-05 0.1244 0.9139
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Interc: 0 0 -nan
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direct_clk 0 0 -nan
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mux1 0 0 -nan
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mux2 0 0 -nan
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frac_logic 3.388e-07 0.001254 0 Transistor Auto-Size
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Bufs/Wires 3.388e-07 0.001254 0
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Interc: 0 0 -nan
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mux1 0 0 -nan
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mux2 0 0 -nan
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frac_lut6 0 0 -nan Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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adder_phy 0 0 -nan Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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ff_phy 3.327e-05 0.1232 0.9232 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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Mode:n2_lut5 1.741e-05 0.06444 0.7925
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Interc: 0 0 -nan
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lut5inter 1.741e-05 0.06444 0.7925 Transistor Auto-Size
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Bufs/Wires 5.658e-07 0.002095 0.6977
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Interc: 0 0 -nan
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complete1 0 0 -nan
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ble5 1.684e-05 0.06235 0.7956 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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Mode:blut5 1.12e-05 0.04146 0.8091
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Interc: 0 0 -nan
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flut5 1.12e-05 0.04146 0.8091 Transistor Auto-Size
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Bufs/Wires 2.007e-07 0.000743 0.7628
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Interc: 2.646e-07 0.0009797 0.684
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mux1 2.646e-07 0.0009797 0.684
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lut5 1.655e-06 0.006127 0.2417 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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Mode:wire 0 0 -nan
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Interc: 0 0 -nan
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complete:lut5 0 0 -nan
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Mode:lut5 1.655e-06 0.006127 0.2417
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Interc: 0 0 -nan
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lut 1.655e-06 0.006127 0.2417 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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ff 9.079e-06 0.03361 0.9173 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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Mode:arithmetic 5.641e-06 0.02088 0.7689
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Interc: 0 0 -nan
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arithmetic 5.641e-06 0.02088 0.7689 Transistor Auto-Size
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Bufs/Wires 3.732e-07 0.001382 0.7081
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Interc: 1.399e-07 0.0005179 0.708
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sumout 1.399e-07 0.0005179 0.708
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lut4 7.913e-07 0.00293 0 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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Mode:wire 0 0 -nan
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Interc: 0 0 -nan
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complete:lut4 0 0 -nan
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Mode:lut4 7.913e-07 0.00293 0
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Interc: 0 0 -nan
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lut 7.913e-07 0.00293 0 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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adder 0 0 -nan Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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ff 4.336e-06 0.01606 0.9163 Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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Mode:n1_lut6 0 0 -nan
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Interc: 0 0 -nan
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ble6 0 0 -nan Transistor Auto-Size
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Bufs/Wires 0 0 -nan
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Interc: 0 0 -nan
|
||||||
|
mux1 0 0 -nan
|
||||||
|
lut6 0 0 -nan Transistor Auto-Size
|
||||||
|
Bufs/Wires 0 0 -nan
|
||||||
|
Mode:wire 0 0 -nan
|
||||||
|
Interc: 0 0 -nan
|
||||||
|
complete:lut6 0 0 -nan
|
||||||
|
Mode:lut6 0 0 -nan
|
||||||
|
Interc: 0 0 -nan
|
||||||
|
lut 0 0 -nan Transistor Auto-Size
|
||||||
|
Bufs/Wires 0 0 -nan
|
||||||
|
ff 0 0 -nan Transistor Auto-Size
|
||||||
|
Bufs/Wires 0 0 -nan
|
||||||
|
Mode:shift_register 1.134e-07 0.0004199 0.7826
|
||||||
|
Interc: 0 0 -nan
|
||||||
|
ble_shift 1.134e-07 0.0004199 0.7826 Transistor Auto-Size
|
||||||
|
Bufs/Wires 1.134e-07 0.0004199 0.7826
|
||||||
|
Interc: 0 0 -nan
|
||||||
|
direct3 0 0 -nan
|
||||||
|
ff 0 0 -nan Transistor Auto-Size
|
||||||
|
Bufs/Wires 0 0 -nan
|
||||||
|
|
||||||
|
|
@ -0,0 +1,78 @@
|
||||||
|
////////////////////////////////////////////////////////
|
||||||
|
// //
|
||||||
|
// Benchmark using all modes of k8 architecture //
|
||||||
|
// //
|
||||||
|
////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
`timescale 1 ns/ 1 ps
|
||||||
|
|
||||||
|
module test_modes(
|
||||||
|
clk,
|
||||||
|
a_0,
|
||||||
|
a_1,
|
||||||
|
a_2,
|
||||||
|
a_3,
|
||||||
|
b_0,
|
||||||
|
b_1,
|
||||||
|
b_2,
|
||||||
|
b_3,
|
||||||
|
cin,
|
||||||
|
e,
|
||||||
|
f,
|
||||||
|
g,
|
||||||
|
sum_0,
|
||||||
|
sum_1,
|
||||||
|
sum_2,
|
||||||
|
sum_3,
|
||||||
|
cout,
|
||||||
|
x,
|
||||||
|
y,
|
||||||
|
z );
|
||||||
|
|
||||||
|
input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g;
|
||||||
|
output reg sum_0, sum_1, sum_2, sum_3, cout;
|
||||||
|
output wire x, y, z;
|
||||||
|
|
||||||
|
wire d0;
|
||||||
|
wire [4:0] n0;
|
||||||
|
wire [3:0] a, b;
|
||||||
|
reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin;
|
||||||
|
|
||||||
|
assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0};
|
||||||
|
assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0};
|
||||||
|
assign d0 = (e && g) || !f;
|
||||||
|
assign n0 = a + b + reg_cin;
|
||||||
|
assign x = reg3;
|
||||||
|
assign y = reg7;
|
||||||
|
assign z = reg11;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
reg0 <= d0;
|
||||||
|
reg1 <= reg0;
|
||||||
|
reg2 <= reg1;
|
||||||
|
reg3 <= reg2;
|
||||||
|
reg4 <= reg3;
|
||||||
|
reg5 <= reg4;
|
||||||
|
reg6 <= reg5;
|
||||||
|
reg7 <= reg6;
|
||||||
|
reg8 <= reg7;
|
||||||
|
reg9 <= reg8;
|
||||||
|
reg10 <= reg9;
|
||||||
|
reg11 <= reg10;
|
||||||
|
reg_a_0 <= a_0;
|
||||||
|
reg_a_1 <= a_1;
|
||||||
|
reg_a_2 <= a_2;
|
||||||
|
reg_a_3 <= a_3;
|
||||||
|
reg_b_0 <= b_0;
|
||||||
|
reg_b_1 <= b_1;
|
||||||
|
reg_b_2 <= b_2;
|
||||||
|
reg_b_3 <= b_3;
|
||||||
|
reg_cin <= cin;
|
||||||
|
sum_0 <= n0[0];
|
||||||
|
sum_1 <= n0[1];
|
||||||
|
sum_2 <= n0[2];
|
||||||
|
sum_3 <= n0[3];
|
||||||
|
cout <= n0[4];
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -1,31 +0,0 @@
|
||||||
# Standard Configuration Example
|
|
||||||
[dir_path]
|
|
||||||
script_base = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/scripts/
|
|
||||||
benchmark_dir = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
|
|
||||||
yosys_path = /home/travis/build/LNIS-Projects/OpenFPGA/yosys/yosys
|
|
||||||
odin2_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
|
|
||||||
cirkit_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/cirkit
|
|
||||||
abc_path = /home/travis/build/LNIS-Projects/OpenFPGA/yosys/yosys-abc
|
|
||||||
abc_mccl_path = /home/travis/build/LNIS-Projects/OpenFPGA/abc_with_bb_support/abc
|
|
||||||
abc_with_bb_support_path = /home/travis/build/LNIS-Projects/OpenFPGA/abc_with_bb_support/abc
|
|
||||||
mpack1_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/mpack1
|
|
||||||
m2net_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/m2net
|
|
||||||
mpack2_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/mpack2
|
|
||||||
vpr_path = /home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/vpr
|
|
||||||
rpt_dir = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/results
|
|
||||||
ace_path = /home/travis/build/LNIS-Projects/OpenFPGA/ace2/ace
|
|
||||||
|
|
||||||
[flow_conf]
|
|
||||||
flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
|
|
||||||
vpr_arch = /home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml # temporary path to the architecture
|
|
||||||
#vpr_arch = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/arch/fpga_spice/.travis_k6_N10_sram_chain_HC.xml # Path when Architecture will move
|
|
||||||
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
|
|
||||||
m2net_conf = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
|
|
||||||
mpack2_arch = K6_pattern7_I24.arch
|
|
||||||
power_tech_xml = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
|
|
||||||
|
|
||||||
[csv_tags]
|
|
||||||
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
|
|
||||||
mpack2_tags = BLE Number:|BLE Fill Rate:
|
|
||||||
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
|
|
||||||
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff
|
|
||||||
|
|
@ -3,18 +3,20 @@
|
||||||
set -e
|
set -e
|
||||||
# Make sure a clear start
|
# Make sure a clear start
|
||||||
pwd_path="$PWD"
|
pwd_path="$PWD"
|
||||||
task_name="k6_N10_regression_TT"
|
task_name="k6_N10_regression_0"
|
||||||
config_file="$PWD/configs/regression/${task_name}.conf"
|
config_file="$PWD/configs/regression/${task_name}.conf"
|
||||||
bench_txt="$PWD/benchmarks/List/mcnc_benchmark.txt"
|
bench_txt="$PWD/benchmarks/List/test_modes.txt"
|
||||||
rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv"
|
rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv"
|
||||||
task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}"
|
task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}"
|
||||||
|
|
||||||
verilog_path="${PWD}/regression_MCNC"
|
verilog_path="${PWD}/regression_MCNC"
|
||||||
|
|
||||||
# FPGA-SPICE
|
# FPGA-SPICE
|
||||||
rm -rf ${pwd_path}/results
|
rm -rf ${pwd_path}/results_regression
|
||||||
cd ${pwd_path}/scripts
|
cd ${pwd_path}/scripts
|
||||||
|
|
||||||
|
perl rewrite_path_in_file.pl -i $config_file
|
||||||
|
|
||||||
# SRAM FPGA
|
# SRAM FPGA
|
||||||
# TT case
|
# TT case
|
||||||
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -remove_designs -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -end_flow_with_test -power
|
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -remove_designs -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -end_flow_with_test -power
|
||||||
|
|
|
||||||
|
|
@ -1433,24 +1433,24 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
|
||||||
print "./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log\n";
|
print "./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log\n";
|
||||||
system("./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log");
|
system("./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log");
|
||||||
|
|
||||||
open(F, $log);
|
#open(F, $log);
|
||||||
my @lines=<F>;
|
#my @lines=<F>;
|
||||||
close F;
|
#close F;
|
||||||
my @results = grep(" ", @lines);
|
#my @results = grep(" ", @lines);
|
||||||
if($#results >= 1){
|
#if($#results >= 1){
|
||||||
foreach my $line (0..$#results){
|
# foreach my $line (0..$#results){
|
||||||
print "$results[$line]\n";
|
# print "$results[$line]\n";
|
||||||
}
|
# }
|
||||||
}
|
#}
|
||||||
if ("on" eq $opt_ptr->{vpr_fpga_verilog_dir}) {
|
#if ("on" eq $opt_ptr->{vpr_fpga_verilog_dir}) {
|
||||||
opendir my($dh), $opt_ptr->{vpr_fpga_verilog_dir_val} or die "\nFolder not created!!\n\n";
|
# opendir my($dh), $opt_ptr->{vpr_fpga_verilog_dir_val} or die "\nFolder not created!!\n\n";
|
||||||
my @files = readdir $dh;
|
# my @files = readdir $dh;
|
||||||
closedir $dh;
|
# closedir $dh;
|
||||||
foreach my $file (0..$#files){
|
# foreach my $file (0..$#files){
|
||||||
print "$files[$file]\t";
|
# print "$files[$file]\t";
|
||||||
}
|
# }
|
||||||
print "\n";
|
3 print "\n";
|
||||||
}
|
#}
|
||||||
chdir $cwd;
|
chdir $cwd;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -1866,6 +1866,9 @@ sub run_yosys_vpr_flow($ $ $ $ $)
|
||||||
$rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag";
|
$rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag";
|
||||||
&generate_path($rpt_dir);
|
&generate_path($rpt_dir);
|
||||||
|
|
||||||
|
# Adapt paths on architecture file
|
||||||
|
`perl rewrite_path_in_file.pl -i $vpr_arch`;
|
||||||
|
|
||||||
# Run Yosys flow
|
# Run Yosys flow
|
||||||
$yosys_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark_file";
|
$yosys_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark_file";
|
||||||
$prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_";
|
$prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_";
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,108 @@
|
||||||
|
#!usr/bin/perl -w
|
||||||
|
use strict;
|
||||||
|
use Cwd;
|
||||||
|
#use Shell;
|
||||||
|
use FileHandle;
|
||||||
|
#Use the time
|
||||||
|
use Time::gmtime;
|
||||||
|
|
||||||
|
my $my_file;
|
||||||
|
my $keyword = "OPENFPGAPATHKEYWORD";
|
||||||
|
my $folder_top = "OpenFPGA";
|
||||||
|
|
||||||
|
sub print_usage()
|
||||||
|
{
|
||||||
|
print "Usage:\n";
|
||||||
|
print " perl <script_name.pl> [-options]\n";
|
||||||
|
print " Options:(Mandatory!)\n";
|
||||||
|
print " -i <input_file_path>\n";
|
||||||
|
print "\n";
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
sub opts_read()
|
||||||
|
{
|
||||||
|
if ($#ARGV == -1){
|
||||||
|
print "Error: Not enough input argument!\n";
|
||||||
|
&print_usage();
|
||||||
|
exit(1);
|
||||||
|
} else {
|
||||||
|
for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){
|
||||||
|
if ("-i" eq $ARGV[$iargv]){
|
||||||
|
$my_file = $ARGV[$iargv+1];
|
||||||
|
$iargv++;
|
||||||
|
} else {
|
||||||
|
die "WRONG ARGUMENT";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
sub rewriting_required_check($)
|
||||||
|
{
|
||||||
|
my ($file) = @_;
|
||||||
|
open(F, $file);
|
||||||
|
my @lines=<F>;
|
||||||
|
close F;
|
||||||
|
my $grep_result = grep ($keyword, @lines);
|
||||||
|
if($grep_result >= 1){
|
||||||
|
print "Rewrite needed\n";
|
||||||
|
return 1;
|
||||||
|
} else {
|
||||||
|
print "Rewrite NOT needed\n";
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
sub save_original($)
|
||||||
|
{
|
||||||
|
my ($template) = @_;
|
||||||
|
my $renamed_template = "$template".".bak";
|
||||||
|
rename($template, $renamed_template);
|
||||||
|
|
||||||
|
return $renamed_template;
|
||||||
|
}
|
||||||
|
|
||||||
|
sub findPath(){
|
||||||
|
my $path;
|
||||||
|
my $dir = cwd;
|
||||||
|
my @folders = split("/", $dir);
|
||||||
|
for(my $count = 0; $count < $#folders; $count++){
|
||||||
|
if($folders[$count] eq ""){
|
||||||
|
} else {
|
||||||
|
$path = "$path"."/"."$folders[$count]";
|
||||||
|
if($folders[$count] eq $folder_top){
|
||||||
|
print "$path\n";
|
||||||
|
return $path;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
die "ERROR: Script launched from the outside of the $folder_top folder!\n";
|
||||||
|
}
|
||||||
|
|
||||||
|
sub create_new($ $)
|
||||||
|
{
|
||||||
|
my ($file, $template) = @_;
|
||||||
|
my $myPath = &findPath();
|
||||||
|
open(IN, '<'.$template);
|
||||||
|
open(OUT, '>'.$file);
|
||||||
|
while(<IN>){
|
||||||
|
$_ =~ s/$keyword/$myPath/g;
|
||||||
|
print OUT $_;
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
sub main()
|
||||||
|
{
|
||||||
|
&opts_read();
|
||||||
|
my $rewrite_needed = &rewriting_required_check($my_file);
|
||||||
|
if($rewrite_needed == 1){
|
||||||
|
my $template_file = &save_original($my_file);
|
||||||
|
&create_new($my_file, $template_file);
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
&main();
|
||||||
24
vpr7_x2p/vpr/.regression_verilog.sh → vpr7_x2p/vpr/regression_verilog.sh
Executable file → Normal file
24
vpr7_x2p/vpr/.regression_verilog.sh → vpr7_x2p/vpr/regression_verilog.sh
Executable file → Normal file
|
|
@ -8,24 +8,10 @@ verilog_output_dirname="${benchmark}_Verilog"
|
||||||
verilog_output_dirpath="$PWD"
|
verilog_output_dirpath="$PWD"
|
||||||
modelsim_ini_file="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini"
|
modelsim_ini_file="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini"
|
||||||
# VPR critical inputs
|
# VPR critical inputs
|
||||||
#set arch_xml_file=ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml
|
arch_xml_file="OPENFPGAPATHKEYWORD/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
|
||||||
#set arch_xml_file=ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
|
blif_file="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
|
||||||
arch_xml_file="ARCH/.travis_k6_N10_sram_chain_HC.xml"
|
act_file="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
|
||||||
#set arch_xml_file=ARCH/ed_stdcell.xml
|
verilog_reference="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
|
||||||
#set arch_xml_file=ARCH/k6_N10_sram_chain_FC_tsmc40.xml
|
|
||||||
#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml
|
|
||||||
#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml
|
|
||||||
#set arch_xml_file=ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml
|
|
||||||
#set verilog_reference=${PWD}/Circuits/alu4_K6_N10_ace.v
|
|
||||||
#set blif_file=Circuits/shiftReg.blif
|
|
||||||
#set act_file=Circuits/shiftReg.act
|
|
||||||
blif_file="Circuits/$benchmark.blif"
|
|
||||||
act_file="Circuits/$benchmark.act "
|
|
||||||
verilog_reference="${PWD}/Circuits/$benchmark.v"
|
|
||||||
#set blif_file=Circuits/frisc.blif
|
|
||||||
#set act_file=Circuits/frisc.act
|
|
||||||
#set blif_file=Circuits/elliptic.blif
|
|
||||||
#set act_file=Circuits/elliptic.act
|
|
||||||
vpr_route_chan_width="200"
|
vpr_route_chan_width="200"
|
||||||
|
|
||||||
# Step A: Make sure a clean start
|
# Step A: Make sure a clean start
|
||||||
|
|
@ -37,7 +23,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname
|
||||||
|
|
||||||
# Run VPR
|
# Run VPR
|
||||||
#valgrind
|
#valgrind
|
||||||
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml #--fpga_verilog_print_sdc_analysis --fpga_verilog_print_sdc_pnr
|
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr #--fpga_verilog_print_sdc_analysis
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
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Reference in New Issue