Added additional PATH variables
This commit is contained in:
parent
f54a8522fa
commit
a25124b58c
|
@ -50,6 +50,11 @@ args = parser.parse_args()
|
||||||
task_script_dir = os.path.dirname(os.path.abspath(__file__))
|
task_script_dir = os.path.dirname(os.path.abspath(__file__))
|
||||||
script_env_vars = ({"PATH": {
|
script_env_vars = ({"PATH": {
|
||||||
"OPENFPGA_FLOW_PATH": task_script_dir,
|
"OPENFPGA_FLOW_PATH": task_script_dir,
|
||||||
|
"ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
|
||||||
|
"BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
|
||||||
|
"TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
|
||||||
|
"SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
|
||||||
|
"VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"),
|
||||||
"OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir,
|
"OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir,
|
||||||
os.pardir))}})
|
os.pardir))}})
|
||||||
config = ConfigParser(interpolation=ExtendedInterpolation())
|
config = ConfigParser(interpolation=ExtendedInterpolation())
|
||||||
|
@ -153,7 +158,7 @@ def generate_each_task_actions(taskname):
|
||||||
|
|
||||||
# Get Flow information
|
# Get Flow information
|
||||||
logger.info('Running "%s" flow' %
|
logger.info('Running "%s" flow' %
|
||||||
GeneralSection.get("fpga_flow", fallback="yosys_vpr"))
|
GeneralSection.get("fpga_flow", fallback="yosys_vpr"))
|
||||||
|
|
||||||
# Check if specified benchmark files exist
|
# Check if specified benchmark files exist
|
||||||
benchmark_list = []
|
benchmark_list = []
|
||||||
|
@ -184,7 +189,6 @@ def generate_each_task_actions(taskname):
|
||||||
CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
|
CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
|
||||||
fallback=chan_width_common)
|
fallback=chan_width_common)
|
||||||
|
|
||||||
|
|
||||||
if GeneralSection.get("fpga_flow") == "vpr_blif":
|
if GeneralSection.get("fpga_flow") == "vpr_blif":
|
||||||
# Check if activity file exist
|
# Check if activity file exist
|
||||||
if not SynthSection.get(bech_name+"_act"):
|
if not SynthSection.get(bech_name+"_act"):
|
||||||
|
|
Loading…
Reference in New Issue