From a1eaacf5a81b905f4e0198739dea106f99751b3c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Oct 2021 12:12:15 -0700 Subject: [PATCH] [Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency --- .../fixed_shift_register_clock_freq/config/task.conf | 9 --------- 1 file changed, 9 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq/config/task.conf index 2e4a821ec..7a75ee299 100644 --- a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq/config/task.conf @@ -28,18 +28,9 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_chan_width = 300 - -bench1_top = or2 -bench1_chan_width = 300 - -bench2_top = and2_latch -bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=