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add configurable child list to module manager

This commit is contained in:
tangxifan 2019-10-23 15:44:13 -06:00
parent 12162a02bc
commit a18f1305cd
10 changed files with 117 additions and 155 deletions
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36
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
View File

@ -63,6 +63,22 @@ std::vector<size_t> ModuleManager::child_module_instances(const ModuleId& parent
return instance_range;
}
/* Find all the configurable child modules under a parent module */
std::vector<ModuleId> ModuleManager::configurable_children(const ModuleId& parent_module) const {
/* Validate the module_id */
VTR_ASSERT(valid_module_id(parent_module));
return configurable_children_[parent_module];
}
/* Find all the instances of configurable child modules under a parent module */
std::vector<size_t> ModuleManager::configurable_child_instances(const ModuleId& parent_module) const {
/* Validate the module_id */
VTR_ASSERT(valid_module_id(parent_module));
return configurable_child_instances_[parent_module];
}
/* Find the source ids of modules */
ModuleManager::module_net_src_range ModuleManager::module_net_sources(const ModuleId& module, const ModuleNetId& net) const {
/* Validate the module_id */
@ -381,6 +397,8 @@ ModuleId ModuleManager::add_module(const std::string& name) {
children_.emplace_back();
num_child_instances_.emplace_back();
child_instance_names_.emplace_back();
configurable_children_.emplace_back();
configurable_child_instances_.emplace_back();
port_ids_.emplace_back();
ports_.emplace_back();
@ -530,6 +548,24 @@ void ModuleManager::set_child_instance_name(const ModuleId& parent_module,
child_instance_names_[parent_module][child_index][instance_id] = instance_name;
}
/* Add a configurable child module to module
* Note: this function should be called after add_child_module!
* It will check if the child module does exist in the parent module
* And the instance id is in range or not
*/
void ModuleManager::add_configurable_child(const ModuleId& parent_module,
const ModuleId& child_module,
const size_t& child_instance) {
/* Validate the id of both parent and child modules */
VTR_ASSERT ( valid_module_id(parent_module) );
VTR_ASSERT ( valid_module_id(child_module) );
/* Ensure that the instance id is in range */
VTR_ASSERT ( child_instance < num_instance(parent_module, child_module));
configurable_children_[parent_module].push_back(child_module);
configurable_child_instances_[parent_module].push_back(child_instance);
}
/* Add a net to the connection graph of the module */
ModuleNetId ModuleManager::create_module_net(const ModuleId& module) {
/* Validate the module id */

15
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h
View File

@ -60,6 +60,10 @@ class ModuleManager {
std::vector<ModuleId> child_modules(const ModuleId& parent_module) const;
/* Find all the instances under a parent module */
std::vector<size_t> child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const;
/* Find all the configurable child modules under a parent module */
std::vector<ModuleId> configurable_children(const ModuleId& parent_module) const;
/* Find all the instances of configurable child modules under a parent module */
std::vector<size_t> configurable_child_instances(const ModuleId& parent_module) const;
/* Find the source ids of modules */
module_net_src_range module_net_sources(const ModuleId& module, const ModuleNetId& net) const;
/* Find the sink ids of modules */
@ -135,6 +139,8 @@ class ModuleManager {
void add_child_module(const ModuleId& parent_module, const ModuleId& child_module);
/* Set the instance name of a child module */
void set_child_instance_name(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id, const std::string& instance_name);
/* Add a configurable child module to module */
void add_configurable_child(const ModuleId& module, const ModuleId& child_module, const size_t& child_instance);
/* Add a net to the connection graph of the module */
ModuleNetId create_module_net(const ModuleId& module);
/* Set the name of net */
@ -165,6 +171,15 @@ class ModuleManager {
vtr::vector<ModuleId, std::vector<size_t>> num_child_instances_; /* Number of children instance in each child module */
vtr::vector<ModuleId, std::vector<std::vector<std::string>>> child_instance_names_; /* Number of children instance in each child module */
/* Configurable child modules are used to record the position of configurable modules in bitstream
* The sequence of children in the list denotes which one is configured first, etc.
* Note that the sequence can be totally different from the children_ list
* This is really dependent how the configuration protocol is organized
* which should be made by users/designers
*/
vtr::vector<ModuleId, std::vector<ModuleId>> configurable_children_; /* Child modules with configurable memory bits that this module contain */
vtr::vector<ModuleId, std::vector<size_t>> configurable_child_instances_; /* Instances of child modules with configurable memory bits that this module contain */
/* Port-level data */
vtr::vector<ModuleId, vtr::vector<ModulePortId, ModulePortId>> port_ids_; /* List of ports for each Module */
vtr::vector<ModuleId, vtr::vector<ModulePortId, BasicPort>> ports_; /* List of ports for each Module */

30
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
View File

@ -583,10 +583,8 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
*********************************************************************/
void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type) {
for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) {
for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
ModulePortId net_src_port_id;
@ -604,20 +602,20 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id = memory_modules[mem_index];
net_sink_instance_id = memory_instances[mem_index];
net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
net_src_module_id = memory_modules[mem_index - 1];
net_src_instance_id = memory_instances[mem_index - 1];
net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1];
net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = generate_configuration_chain_head_name();
net_sink_module_id = memory_modules[mem_index];
net_sink_instance_id = memory_instances[mem_index];
net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -645,8 +643,8 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
*/
/* Find the port name of previous memory module */
std::string src_port_name = generate_configuration_chain_tail_name();
ModuleId net_src_module_id = memory_modules.back();
size_t net_src_instance_id = memory_instances.back();
ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back();
size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back();
ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
@ -720,18 +718,13 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
static
void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type) {
/* Ensure that the size of memory_model vector matches the memory_module vector */
VTR_ASSERT(memory_modules.size() == memory_instances.size());
switch (sram_orgz_type) {
case SPICE_SRAM_STANDALONE:
/* Nothing to do */
break;
case SPICE_SRAM_SCAN_CHAIN: {
add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, memory_modules, memory_instances, sram_orgz_type);
add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, sram_orgz_type);
break;
}
case SPICE_SRAM_MEMORY_BANK:
@ -802,14 +795,11 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
*******************************************************************/
void add_module_nets_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type,
const e_spice_model_design_tech& mem_tech) {
switch (mem_tech) {
case SPICE_MODEL_DESIGN_CMOS:
add_module_nets_cmos_memory_config_bus(module_manager, parent_module,
memory_modules, memory_instances,
sram_orgz_type);
break;
case SPICE_MODEL_DESIGN_RRAM:

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h
View File

@ -71,14 +71,10 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type);
void add_module_nets_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type,
const e_spice_model_design_tech& mem_tech);

20
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
View File

@ -359,15 +359,13 @@ void build_primitive_block_module(ModuleManager& module_manager,
memory_module, memory_instance_id,
circuit_lib, primitive_model);
/* Record memory-related information */
memory_modules.push_back(memory_module);
memory_instances.push_back(memory_instance_id);
module_manager.add_configurable_child(primitive_module, memory_module, memory_instance_id);
}
/* Add all the nets to connect configuration ports from memory module to primitive modules
* This is a one-shot addition that covers all the memory modules in this primitive module!
*/
if (false == memory_modules.empty()) {
add_module_nets_memory_config_bus(module_manager, primitive_module,
memory_modules, memory_instances,
sram_orgz_type, circuit_lib.design_tech_type(sram_model));
}
}
@ -908,8 +906,7 @@ void rec_build_physical_block_modules(ModuleManager& module_manager,
if (0 < find_module_num_config_bits(module_manager, child_pb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
memory_modules.push_back(child_pb_module);
memory_instances.push_back(child_instance_id);
module_manager.add_configurable_child(pb_module, child_pb_module, child_instance_id);
}
}
}
@ -958,7 +955,6 @@ void rec_build_physical_block_modules(ModuleManager& module_manager,
*/
if (false == memory_modules.empty()) {
add_module_nets_memory_config_bus(module_manager, pb_module,
memory_modules, memory_instances,
sram_orgz_type, circuit_lib.design_tech_type(sram_model));
}
}
@ -1001,12 +997,6 @@ void build_grid_module(ModuleManager& module_manager,
ModuleId grid_module = module_manager.add_module(grid_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
/* Vectors to record all the memory modules have been added
* They are used to add module nets of configuration bus
*/
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
/* Generate the name of the Verilog module for this pb_type */
std::string pb_module_name_prefix(grid_verilog_file_name_prefix);
std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side);
@ -1023,8 +1013,7 @@ void build_grid_module(ModuleManager& module_manager,
if (0 < find_module_num_config_bits(module_manager, pb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
memory_modules.push_back(pb_module);
memory_instances.push_back(pb_instance_id);
module_manager.add_configurable_child(grid_module, pb_module, pb_instance_id);
}
}
@ -1072,9 +1061,8 @@ void build_grid_module(ModuleManager& module_manager,
/* Add module nets to connect memory cells inside
* This is a one-shot addition that covers all the memory modules in this pb module!
*/
if (false == memory_modules.empty()) {
if (0 < module_manager.configurable_children(grid_module).size()) {
add_module_nets_memory_config_bus(module_manager, grid_module,
memory_modules, memory_instances,
sram_orgz_type, circuit_lib.design_tech_type(sram_model));
}
}

29
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp
View File

@ -153,12 +153,10 @@ void add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager,
static
void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const CircuitLibrary& circuit_lib,
const CircuitPortId& model_input_port,
const CircuitPortId& model_output_port) {
for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) {
for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
ModuleId net_src_module_id;
size_t net_src_instance_id;
ModulePortId net_src_port_id;
@ -176,20 +174,20 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_lib_name(model_input_port);
net_sink_module_id = memory_modules[mem_index];
net_sink_instance_id = memory_instances[mem_index];
net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
} else {
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_lib_name(model_output_port);
net_src_module_id = memory_modules[mem_index - 1];
net_src_instance_id = memory_instances[mem_index - 1];
net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1];
net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1];
net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = circuit_lib.port_lib_name(model_input_port);
net_sink_module_id = memory_modules[mem_index];
net_sink_instance_id = memory_instances[mem_index];
net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
}
@ -217,8 +215,8 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
*/
/* Find the port name of previous memory module */
std::string src_port_name = circuit_lib.port_lib_name(model_output_port);
ModuleId net_src_module_id = memory_modules.back();
size_t net_src_instance_id = memory_instances.back();
ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back();
size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back();
ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
@ -299,6 +297,7 @@ void build_memory_standalone_module(ModuleManager& module_manager,
for (size_t i = 0; i < num_mems; ++i) {
size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
/* Build module nets */
/* Wire inputs of parent module to inputs of child modules */
@ -380,15 +379,11 @@ void build_memory_chain_module(ModuleManager& module_manager,
/* Find the sram module in the module manager */
ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
/* Instanciate each submodule */
for (size_t i = 0; i < num_mems; ++i) {
size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module);
module_manager.add_child_module(mem_module, sram_mem_module);
memory_modules.push_back(sram_mem_module);
memory_instances.push_back(sram_mem_instance);
module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
/* Build module nets to wire outputs of sram modules to outputs of memory module */
for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
@ -405,7 +400,7 @@ void build_memory_chain_module(ModuleManager& module_manager,
}
/* Build module nets to wire the configuration chain */
add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, memory_modules, memory_instances,
add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module,
circuit_lib, sram_input_ports[0], sram_output_ports[0]);

52
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp
View File

@ -229,9 +229,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
t_rr_node* cur_rr_node,
const std::vector<t_rr_node*>& drive_rr_nodes,
const size_t& switch_index,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances) {
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
/* Check current rr_node is CHANX or CHANY*/
VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type));
@ -306,8 +304,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
mem_module, mem_instance_id,
circuit_lib, mux_model);
/* Update memory and instance list */
memory_modules.push_back(mem_module);
memory_instances.push_back(mem_instance_id);
module_manager.add_configurable_child(sb_module, mem_module, mem_instance_id);
}
/*********************************************************************
@ -324,9 +321,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
const std::vector<t_switch_inf>& rr_switches,
const e_side& chan_side,
const size_t& chan_node_id,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances) {
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
std::vector<t_rr_node*> drive_rr_nodes;
/* Get the node */
@ -363,8 +358,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
grids, rr_switches, chan_side, cur_rr_node,
drive_rr_nodes,
cur_rr_node->drive_switches[DEFAULT_SWITCH_ID],
input_port_to_module_nets,
memory_modules, memory_instances);
input_port_to_module_nets);
} /*Nothing should be done else*/
}
@ -497,12 +491,6 @@ void build_switch_block_module(ModuleManager& module_manager,
}
}
/* Vectors to record all the memory modules have been added
* They are used to add module nets of configuration bus
*/
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
/* Add routing multiplexers as child modules */
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
Side side_manager(side);
@ -514,8 +502,7 @@ void build_switch_block_module(ModuleManager& module_manager,
circuit_lib, grids, rr_switches,
side_manager.get_side(),
itrack,
input_port_to_module_nets,
memory_modules, memory_instances);
input_port_to_module_nets);
}
}
}
@ -547,9 +534,8 @@ void build_switch_block_module(ModuleManager& module_manager,
/* Add all the nets to connect configuration ports from memory module to primitive modules
* This is a one-shot addition that covers all the memory modules in this primitive module!
*/
if (false == memory_modules.empty()) {
if (0 < module_manager.configurable_children(sb_module).size()) {
add_module_nets_memory_config_bus(module_manager, sb_module,
memory_modules, memory_instances,
sram_orgz_type, circuit_lib.design_tech_type(sram_model));
}
}
@ -701,9 +687,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
t_rr_node* cur_rr_node,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances) {
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
/* Check current rr_node is an input pin of a CLB */
VTR_ASSERT(IPIN == cur_rr_node->type);
@ -785,8 +769,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
mem_module, mem_instance_id,
circuit_lib, mux_model);
/* Update memory and instance list */
memory_modules.push_back(mem_module);
memory_instances.push_back(mem_instance_id);
module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id);
}
/********************************************************************
@ -805,9 +788,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
const std::vector<std::vector<t_grid_tile>>& grids,
const std::vector<t_switch_inf>& rr_switches,
t_rr_node* src_rr_node,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances) {
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
if (1 > src_rr_node->fan_in) {
return; /* This port has no driver, skip it */
} else if (1 == src_rr_node->fan_in) {
@ -820,8 +801,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
cb_module, rr_gsb, cb_type,
circuit_lib, grids, rr_switches,
src_rr_node,
input_port_to_module_nets,
memory_modules, memory_instances);
input_port_to_module_nets);
} /*Nothing should be done else*/
}
@ -973,12 +953,6 @@ void build_connection_block_module(ModuleManager& module_manager,
}
}
/* Vectors to record all the memory modules have been added
* They are used to add module nets of configuration bus
*/
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
/* TODO: Add sub modules of routing multiplexers or direct interconnect*/
for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
enum e_side cb_ipin_side = cb_ipin_sides[iside];
@ -987,8 +961,7 @@ void build_connection_block_module(ModuleManager& module_manager,
cb_module, rr_gsb, cb_type,
circuit_lib, grids, rr_switches,
rr_gsb.get_ipin_node(cb_ipin_side, inode),
input_port_to_module_nets,
memory_modules, memory_instances);
input_port_to_module_nets);
}
}
@ -1019,9 +992,8 @@ void build_connection_block_module(ModuleManager& module_manager,
/* Add all the nets to connect configuration ports from memory module to primitive modules
* This is a one-shot addition that covers all the memory modules in this primitive module!
*/
if (false == memory_modules.empty()) {
if (0 < module_manager.configurable_children(cb_module).size()) {
add_module_nets_memory_config_bus(module_manager, cb_module,
memory_modules, memory_instances,
sram_orgz_type, circuit_lib.design_tech_type(sram_model));
}
}

14
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp
View File

@ -864,26 +864,18 @@ void build_top_module(ModuleManager& module_manager,
add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
}
/* Vectors to record all the memory modules have been added
* They are used to add module nets of configuration bus
*/
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
/* Organize the list of memory modules and instances */
organize_top_module_memory_modules(module_manager,
organize_top_module_memory_modules(module_manager, top_module,
circuit_lib, sram_orgz_type, sram_model,
device_size, grids, grid_instance_ids,
L_device_rr_gsb, sb_instance_ids, cb_instance_ids,
compact_routing_hierarchy,
memory_modules, memory_instances);
compact_routing_hierarchy);
/* Add module nets to connect memory cells inside
* This is a one-shot addition that covers all the memory modules in this pb module!
*/
if (false == memory_modules.empty()) {
if (0 < module_manager.configurable_children(top_module).size()) {
add_top_module_nets_memory_config_bus(module_manager, top_module,
memory_modules, memory_instances,
sram_orgz_type, circuit_lib.design_tech_type(sram_model));
}
}

63
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp
View File

@ -20,7 +20,8 @@
* module
*******************************************************************/
static
void organize_top_module_tile_cb_modules(const ModuleManager& module_manager,
void organize_top_module_tile_cb_modules(ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
@ -28,9 +29,7 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const bool& compact_routing_hierarchy,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances) {
const bool& compact_routing_hierarchy) {
/* If the CB does not exist, we can skip addition */
if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))
|| (true != rr_gsb.is_cb_exist(cb_type))) {
@ -55,8 +54,7 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager,
if (0 < find_module_num_config_bits(module_manager, cb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
memory_modules.push_back(cb_module);
memory_instances.push_back(cb_instance_ids[cb_coord.x()][cb_coord.y()]);
module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[cb_coord.x()][cb_coord.y()]);
}
}
@ -67,7 +65,8 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager,
* module
*******************************************************************/
static
void organize_top_module_tile_memory_modules(const ModuleManager& module_manager,
void organize_top_module_tile_memory_modules(ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
@ -78,9 +77,7 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager
const std::map<t_rr_type, std::vector<std::vector<size_t>>>& cb_instance_ids,
const bool& compact_routing_hierarchy,
const vtr::Point<size_t>& tile_coord,
const e_side& tile_border_side,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances) {
const e_side& tile_border_side) {
vtr::Point<size_t> gsb_coord_range(L_device_rr_gsb.get_gsb_range().get_x(), L_device_rr_gsb.get_gsb_range().get_y());
@ -110,24 +107,21 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager
if (0 < find_module_num_config_bits(module_manager, sb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
memory_modules.push_back(sb_module);
memory_instances.push_back(sb_instance_ids[sb_coord.x()][sb_coord.y()]);
module_manager.add_configurable_child(top_module, sb_module, sb_instance_ids[sb_coord.x()][sb_coord.y()]);
}
/* Try to find and add CBX and CBY */
organize_top_module_tile_cb_modules(module_manager, circuit_lib,
organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib,
sram_orgz_type, sram_model,
cb_instance_ids.at(CHANX),
L_device_rr_gsb, rr_gsb, CHANX,
compact_routing_hierarchy,
memory_modules, memory_instances);
compact_routing_hierarchy);
organize_top_module_tile_cb_modules(module_manager, circuit_lib,
organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib,
sram_orgz_type, sram_model,
cb_instance_ids.at(CHANY),
L_device_rr_gsb, rr_gsb, CHANY,
compact_routing_hierarchy,
memory_modules, memory_instances);
compact_routing_hierarchy);
}
/* Find the module name for this type of grid */
@ -143,8 +137,7 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager
if (0 < find_module_num_config_bits(module_manager, grid_module,
circuit_lib, sram_model,
sram_orgz_type)) {
memory_modules.push_back(grid_module);
memory_instances.push_back(grid_instance_ids[tile_coord.x()][tile_coord.y()]);
module_manager.add_configurable_child(top_module, grid_module, grid_instance_ids[tile_coord.x()][tile_coord.y()]);
}
}
@ -207,7 +200,8 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager
* +---------------+----------+
*
*******************************************************************/
void organize_top_module_memory_modules(const ModuleManager& module_manager,
void organize_top_module_memory_modules(ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
@ -217,12 +211,9 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const std::vector<std::vector<size_t>>& sb_instance_ids,
const std::map<t_rr_type, std::vector<std::vector<size_t>>>& cb_instance_ids,
const bool& compact_routing_hierarchy,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances) {
const bool& compact_routing_hierarchy) {
/* Ensure clean vectors to return */
VTR_ASSERT(true == memory_modules.empty());
VTR_ASSERT(true == memory_instances.empty());
VTR_ASSERT(true == module_manager.configurable_children(top_module).empty());
/* First, organize the I/O tiles on the border */
/* Special for the I/O tileas on RIGHT and BOTTOM,
@ -254,13 +245,12 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager,
for (const e_side& io_side : io_sides) {
for (const vtr::Point<size_t>& io_coord : io_coords[io_side]) {
/* Identify the GSB that surrounds the grid */
organize_top_module_tile_memory_modules(module_manager,
organize_top_module_tile_memory_modules(module_manager, top_module,
circuit_lib, sram_orgz_type, sram_model,
grids, grid_instance_ids,
L_device_rr_gsb, sb_instance_ids, cb_instance_ids,
compact_routing_hierarchy,
io_coord, io_side,
memory_modules, memory_instances);
io_coord, io_side);
}
}
@ -285,13 +275,12 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager,
}
for (const vtr::Point<size_t>& core_coord : core_coords) {
organize_top_module_tile_memory_modules(module_manager,
organize_top_module_tile_memory_modules(module_manager, top_module,
circuit_lib, sram_orgz_type, sram_model,
grids, grid_instance_ids,
L_device_rr_gsb, sb_instance_ids, cb_instance_ids,
compact_routing_hierarchy,
core_coord, NUM_SIDES,
memory_modules, memory_instances);
core_coord, NUM_SIDES);
}
}
@ -343,18 +332,13 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager,
static
void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type) {
/* Ensure that the size of memory_model vector matches the memory_module vector */
VTR_ASSERT(memory_modules.size() == memory_instances.size());
switch (sram_orgz_type) {
case SPICE_SRAM_STANDALONE:
/* Nothing to do */
break;
case SPICE_SRAM_SCAN_CHAIN: {
add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, memory_modules, memory_instances, sram_orgz_type);
add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, SPICE_SRAM_SCAN_CHAIN);
break;
}
case SPICE_SRAM_MEMORY_BANK:
@ -402,14 +386,11 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
*******************************************************************/
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type,
const e_spice_model_design_tech& mem_tech) {
switch (mem_tech) {
case SPICE_MODEL_DESIGN_CMOS:
add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module,
memory_modules, memory_instances,
sram_orgz_type);
break;
case SPICE_MODEL_DESIGN_RRAM:

9
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h
View File

@ -8,7 +8,8 @@
#include "circuit_library.h"
#include "rr_blocks.h"
void organize_top_module_memory_modules(const ModuleManager& module_manager,
void organize_top_module_memory_modules(ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model,
@ -18,14 +19,10 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const std::vector<std::vector<size_t>>& sb_instance_ids,
const std::map<t_rr_type, std::vector<std::vector<size_t>>>& cb_instance_ids,
const bool& compact_routing_hierarchy,
std::vector<ModuleId>& memory_modules,
std::vector<size_t>& memory_instances);
const bool& compact_routing_hierarchy);
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type,
const e_spice_model_design_tech& mem_tech);