riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[test] update arch to allow clock access on CLB inputs

This commit is contained in:
tangxifan 2024-07-09 20:59:44 -07:00
parent 0f78803759
commit a16b3df063
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
View File

@ -107,11 +107,12 @@
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<!-- Note that clb.I[0:5] are assigned on right side for clock pins of programmable clock network to access. The clb.I[6:11] may not be accessible through programmable clock network. This is a limitation in current clock network -->
<pinlocations pattern="custom">
<loc side="left"/>
<loc side="top"/>
<loc side="right">clb.reset clb.clk clb.O[4:7] clb.I[6:11]</loc>
<loc side="bottom">clb.O[0:3] clb.I[0:5]</loc>
<loc side="right">clb.reset clb.clk clb.O[0:3] clb.I[0:5]</loc>
<loc side="bottom">clb.O[4:7] clb.I[6:11]</loc>
</pinlocations>
</sub_tile>
</tile>