From a15798a4e1891f44ea305617f3230e9c862e7dc8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 7 Oct 2021 14:42:21 -0700 Subject: [PATCH] [Lib] Upgrade fabric key data structure to support shift register bank definitions --- libopenfpga/libfabrickey/src/fabric_key.cpp | 70 +++++++++++++++++++ libopenfpga/libfabrickey/src/fabric_key.h | 43 ++++++++++++ libopenfpga/libfabrickey/src/fabric_key_fwd.h | 4 ++ 3 files changed, 117 insertions(+) diff --git a/libopenfpga/libfabrickey/src/fabric_key.cpp b/libopenfpga/libfabrickey/src/fabric_key.cpp index d15c86e56..bd61a3103 100644 --- a/libopenfpga/libfabrickey/src/fabric_key.cpp +++ b/libopenfpga/libfabrickey/src/fabric_key.cpp @@ -27,6 +27,16 @@ FabricKey::fabric_region_range FabricKey::regions() const { return vtr::make_range(region_ids_.begin(), region_ids_.end()); } +FabricKey::fabric_bit_line_bank_range FabricKey::bl_banks(const FabricRegionId& region_id) const { + VTR_ASSERT(valid_region_id(region_id)); + return vtr::make_range(bl_bank_ids_[region_id].begin(), bl_bank_ids_[region_id].end()); +} + +FabricKey::fabric_word_line_bank_range FabricKey::wl_banks(const FabricRegionId& region_id) const { + VTR_ASSERT(valid_region_id(region_id)); + return vtr::make_range(wl_bank_ids_[region_id].begin(), wl_bank_ids_[region_id].end()); +} + /************************************************************************ * Public Accessors : Basic data query ***********************************************************************/ @@ -64,6 +74,16 @@ bool FabricKey::empty() const { return 0 == key_ids_.size(); } +std::vector FabricKey::bl_bank_data_ports(const FabricRegionId& region_id, const FabricBitLineBankId& bank_id) const { + VTR_ASSERT(valid_bl_bank_id(region_id, bank_id)); + return bl_bank_data_ports_[region_id][bank_id]; +} + +std::vector FabricKey::wl_bank_data_ports(const FabricRegionId& region_id, const FabricWordLineBankId& bank_id) const { + VTR_ASSERT(valid_wl_bank_id(region_id, bank_id)); + return wl_bank_data_ports_[region_id][bank_id]; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -178,6 +198,42 @@ void FabricKey::set_key_coordinate(const FabricKeyId& key_id, key_coordinates_[key_id] = coord; } +FabricBitLineBankId FabricKey::create_bl_shift_register_bank(const FabricRegionId& region_id) { + VTR_ASSERT(valid_region_id(region_id)); + + /* Create a new id */ + FabricBitLineBankId bank = FabricBitLineBankId(bl_bank_ids_[region_id].size()); + bl_bank_ids_[region_id].push_back(bank); + bl_bank_data_ports_[region_id].emplace_back(); + + return bank; +} + +void FabricKey::add_data_port_to_bl_shift_register_bank(const FabricRegionId& region_id, + const FabricBitLineBankId& bank_id, + const openfpga::BasicPort& data_port) { + VTR_ASSERT(valid_bl_bank_id(region_id, bank_id)); + bl_bank_data_ports_[region_id][bank_id].push_back(data_port); +} + +FabricWordLineBankId FabricKey::create_wl_shift_register_bank(const FabricRegionId& region_id) { + VTR_ASSERT(valid_region_id(region_id)); + + /* Create a new id */ + FabricWordLineBankId bank = FabricWordLineBankId(wl_bank_ids_[region_id].size()); + wl_bank_ids_[region_id].push_back(bank); + wl_bank_data_ports_[region_id].emplace_back(); + + return bank; +} + +void FabricKey::add_data_port_to_wl_shift_register_bank(const FabricRegionId& region_id, + const FabricWordLineBankId& bank_id, + const openfpga::BasicPort& data_port) { + VTR_ASSERT(valid_wl_bank_id(region_id, bank_id)); + wl_bank_data_ports_[region_id][bank_id].push_back(data_port); +} + /************************************************************************ * Internal invalidators/validators ***********************************************************************/ @@ -193,3 +249,17 @@ bool FabricKey::valid_key_id(const FabricKeyId& key_id) const { bool FabricKey::valid_key_coordinate(const vtr::Point& coord) const { return coord.x() > -1 && coord.y() > -1; } + +bool FabricKey::valid_bl_bank_id(const FabricRegionId& region_id, const FabricBitLineBankId& bank_id) const { + if (!valid_region_id(region_id)) { + return false; + } + return ( size_t(bank_id) < bl_bank_ids_[region_id].size() ) && ( bank_id == bl_bank_ids_[region_id][bank_id] ); +} + +bool FabricKey::valid_wl_bank_id(const FabricRegionId& region_id, const FabricWordLineBankId& bank_id) const { + if (!valid_region_id(region_id)) { + return false; + } + return ( size_t(bank_id) < wl_bank_ids_[region_id].size() ) && ( bank_id == wl_bank_ids_[region_id][bank_id] ); +} diff --git a/libopenfpga/libfabrickey/src/fabric_key.h b/libopenfpga/libfabrickey/src/fabric_key.h index 6e9025f9e..2ce6db061 100644 --- a/libopenfpga/libfabrickey/src/fabric_key.h +++ b/libopenfpga/libfabrickey/src/fabric_key.h @@ -12,6 +12,9 @@ #include "vtr_vector.h" #include "vtr_geometry.h" +/* Headers from openfpgautil library */ +#include "openfpga_port.h" + #include "fabric_key_fwd.h" /******************************************************************** @@ -38,14 +41,20 @@ class FabricKey { public: /* Types */ typedef vtr::vector::const_iterator fabric_key_iterator; typedef vtr::vector::const_iterator fabric_region_iterator; + typedef vtr::vector::const_iterator fabric_bit_line_bank_iterator; + typedef vtr::vector::const_iterator fabric_word_line_bank_iterator; /* Create range */ typedef vtr::Range fabric_region_range; typedef vtr::Range fabric_key_range; + typedef vtr::Range fabric_bit_line_bank_range; + typedef vtr::Range fabric_word_line_bank_range; public: /* Constructors */ FabricKey(); public: /* Accessors: aggregates */ fabric_key_range keys() const; fabric_region_range regions() const; + fabric_bit_line_bank_range bl_banks(const FabricRegionId& region_id) const; + fabric_word_line_bank_range wl_banks(const FabricRegionId& region_id) const; public: /* Public Accessors: Basic data query */ /* Access all the keys of a region */ std::vector region_keys(const FabricRegionId& region_id) const; @@ -65,6 +74,12 @@ class FabricKey { /* Check if there are any keys */ bool empty() const; + /* Return a list of data ports which will be driven by a BL shift register bank */ + std::vector bl_bank_data_ports(const FabricRegionId& region_id, const FabricBitLineBankId& bank_id) const; + + /* Return a list of data ports which will be driven by a WL shift register bank */ + std::vector wl_bank_data_ports(const FabricRegionId& region_id, const FabricWordLineBankId& bank_id) const; + public: /* Public Mutators: model-related */ /* Reserve a number of regions to be memory efficent */ @@ -100,11 +115,29 @@ class FabricKey { void set_key_coordinate(const FabricKeyId& key_id, const vtr::Point& coord); + /* Create a new shift register bank for BLs and return an id */ + FabricBitLineBankId create_bl_shift_register_bank(const FabricRegionId& region_id); + + /* Add a data port to a given BL shift register bank */ + void add_data_port_to_bl_shift_register_bank(const FabricRegionId& region_id, + const FabricBitLineBankId& bank_id, + const openfpga::BasicPort& data_port); + + /* Create a new shift register bank for WLs and return an id */ + FabricWordLineBankId create_wl_shift_register_bank(const FabricRegionId& region_id); + + /* Add a data port to a given WL shift register bank */ + void add_data_port_to_wl_shift_register_bank(const FabricRegionId& region_id, + const FabricWordLineBankId& bank_id, + const openfpga::BasicPort& data_port); + public: /* Public invalidators/validators */ bool valid_region_id(const FabricRegionId& region_id) const; bool valid_key_id(const FabricKeyId& key_id) const; /* Identify if key coordinate is acceptable to fabric key convention */ bool valid_key_coordinate(const vtr::Point& coord) const; + bool valid_bl_bank_id(const FabricRegionId& region_id, const FabricBitLineBankId& bank_id) const; + bool valid_wl_bank_id(const FabricRegionId& region_id, const FabricWordLineBankId& bank_id) const; private: /* Internal data */ /* Unique ids for each region */ vtr::vector region_ids_; @@ -129,6 +162,16 @@ class FabricKey { /* Optional alias for each key, with which a key can also be represented */ vtr::vector key_alias_; + + /* Unique ids for each BL shift register bank */ + vtr::vector> bl_bank_ids_; + /* Data ports to be connected to each BL shift register bank */ + vtr::vector>> bl_bank_data_ports_; + + /* Unique ids for each WL shift register bank */ + vtr::vector> wl_bank_ids_; + /* Data ports to be connected to each WL shift register bank */ + vtr::vector>> wl_bank_data_ports_; }; #endif diff --git a/libopenfpga/libfabrickey/src/fabric_key_fwd.h b/libopenfpga/libfabrickey/src/fabric_key_fwd.h index 249093fd2..7309daa23 100644 --- a/libopenfpga/libfabrickey/src/fabric_key_fwd.h +++ b/libopenfpga/libfabrickey/src/fabric_key_fwd.h @@ -14,9 +14,13 @@ struct fabric_region_id_tag; struct fabric_key_id_tag; +struct fabric_bit_line_bank_id_tag; +struct fabric_word_line_bank_id_tag; typedef vtr::StrongId FabricRegionId; typedef vtr::StrongId FabricKeyId; +typedef vtr::StrongId FabricBitLineBankId; +typedef vtr::StrongId FabricWordLineBankId; /* Short declaration of class */ class FabricKey;