From a0b150f12e6c6682bb65bd8b275bca6659fa9e53 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Mar 2020 14:18:59 -0600 Subject: [PATCH] adding micro architecture using adder chain --- libs/libarchfpga/src/read_xml_arch_file.cpp | 25 +- .../and_k6_frac_adder_chain.openfpga | 59 ++ openfpga/test_vpr_arch/k6_frac_N10_40nm.xml | 3 +- .../k6_frac_N10_adder_chain_40nm.xml | 630 ++++++++++++++++++ 4 files changed, 706 insertions(+), 11 deletions(-) create mode 100644 openfpga/test_script/and_k6_frac_adder_chain.openfpga create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 1c2bba875..b3b4004b2 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2900,21 +2900,26 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& "Unknown property %s for switch block type x\n", Prop); } - Prop = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).value(); - if (strcmp(Prop, "wilton") == 0) { - arch->SBSubType = WILTON; - } else if (strcmp(Prop, "universal") == 0) { - arch->SBSubType = UNIVERSAL; - } else if (strcmp(Prop, "subset") == 0) { - arch->SBSubType = SUBSET; + std::string sub_type_str = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).as_string(""); + /* If not specified, we set the same value as 'type' */ + if (!sub_type_str.empty()) { + if (sub_type_str == std::string("wilton")) { + arch->SBSubType = WILTON; + } else if (sub_type_str == std::string("universal")) { + arch->SBSubType = UNIVERSAL; + } else if (sub_type_str == std::string("subset")) { + arch->SBSubType = SUBSET; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "Unknown property %s for switch block subtype x\n", Prop); + } } else { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), - "Unknown property %s for switch block subtype x\n", Prop); + arch->SBSubType = arch->SBType; } ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block); arch->Fs = get_attribute(Cur, "fs", loc_data, CUSTOM_SWITCHBLOCK_REQD).as_int(3); - arch->subFs = get_attribute(Cur, "sub_fs", loc_data, BoolToReqOpt(false)).as_int(3); + arch->subFs = get_attribute(Cur, "sub_fs", loc_data, BoolToReqOpt(false)).as_int(arch->Fs); Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL); if (Cur) { diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga new file mode 100644 index 000000000..2de7e14ab --- /dev/null +++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga @@ -0,0 +1,59 @@ +# Run VPR for the 'and' design +vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml + +## Read OpenFPGA architecture definition +#read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml +# +## Write out the architecture XML as a proof +##write_openfpga_arch -f ./arch_echo.xml +# +## Annotate the OpenFPGA architecture to VPR data base +#link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose +# +## Check and correct any naming conflicts in the BLIF netlist +#check_netlist_naming_conflict --fix --report ./netlist_renaming.xml +# +## Apply fix-up to clustering nets based on routing results +#pb_pin_fixup --verbose +# +## Apply fix-up to Look-Up Table truth tables based on packing results +#lut_truth_table_fixup #--verbose +# +## Build the module graph +## - Enabled compression on routing architecture modules +## - Enable pin duplication on grid modules +#build_fabric --compress_routing --duplicate_grid_pin #--verbose +# +## Repack the netlist to physical pbs +## This must be done before bitstream generator and testbench generation +## Strongly recommend it is done after all the fix-up have been applied +#repack #--verbose +# +## Build the bitstream +## - Output the fabric-independent bitstream to a file +#build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml +# +## Build fabric-dependent bitstream +#build_fabric_bitstream --verbose +# +## Write the Verilog netlist for FPGA fabric +## - Enable the use of explicit port mapping in Verilog netlist +#write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +# +## Write the Verilog testbench for FPGA fabric +## - We suggest the use of same output directory as fabric Verilog netlists +## - Must specify the reference benchmark file if you want to output any testbenches +## - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +## - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +## - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +#write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini +# +## Write the SDC files for PnR backend +## - Turn on every options here +#write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC +# +## Write the SDC to run timing analysis for a mapped FPGA fabric +#write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis +# +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml index 51f6824f9..8f58cb221 100644 --- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml +++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml @@ -135,6 +135,7 @@ + 1 1 1 1 1 @@ -227,7 +228,7 @@ - + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml new file mode 100644 index 000000000..4bce8ac18 --- /dev/null +++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml @@ -0,0 +1,630 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +