From 2344cdcabc60212a194f1b5d3145d2aa64bfedca Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 21:11:28 -0500 Subject: [PATCH 01/18] merge --- openfpga_flow/scripts/run_fpga_task.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 9d20799df..fa297932e 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -166,9 +166,16 @@ def generate_each_task_actions(taskname): """ # Check if task directory exists and consistent - curr_task_dir = os.path.join(gc["task_dir"], *(taskname)) - if not os.path.isdir(curr_task_dir): + local_tasks = os.path.join(*(taskname)) + repo_tasks = os.path.join(gc["task_dir"], *(taskname)) + if os.path.isdir(local_tasks): + os.chdir(local_tasks) + curr_task_dir = os.path.abspath(os.getcwd()) + elif os.path.isdir(repo_tasks): + curr_task_dir = repo_tasks + else: clean_up_and_exit("Task directory [%s] not found" % curr_task_dir) + os.chdir(curr_task_dir) curr_task_conf_file = os.path.join(curr_task_dir, "config", "task.conf") From 0c6d27cf7ea056db2c82fa0b1578dd7faf9df469 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 21:26:48 -0500 Subject: [PATCH 02/18] merge for consideration; --- ...tdcell_mux_40nm_openfpga_synthesizable.xml | 223 ++++++++++++++++++ .../openfpga_cell_library/verilog/buf4.v | 29 +++ .../openfpga_cell_library/verilog/dffr.v | 35 +++ .../openfpga_cell_library/verilog/dffsrq.v | 36 +++ .../openfpga_cell_library/verilog/inv.v | 29 +++ 5 files changed, 352 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml create mode 100644 openfpga_flow/openfpga_cell_library/verilog/buf4.v create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffr.v create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffsrq.v create mode 100644 openfpga_flow/openfpga_cell_library/verilog/inv.v diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml new file mode 100644 index 000000000..6d7b080f1 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml @@ -0,0 +1,223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/buf4.v b/openfpga_flow/openfpga_cell_library/verilog/buf4.v new file mode 100644 index 000000000..a9f0585bc --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/buf4.v @@ -0,0 +1,29 @@ +// ----- Verilog module for buf4 ----- +module buf4(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + //assign out = (in === 1'bz)? $random : in; + assign out = in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in[0] => out[0]) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for buf4 ----- + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffr.v b/openfpga_flow/openfpga_cell_library/verilog/dffr.v new file mode 100644 index 000000000..051fa71fb --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dffr.v @@ -0,0 +1,35 @@ +module DFFR(RST, + CK, + D, + Q, + QN); +//----- GLOBAL PORTS ----- +input [0:0] RST; +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output reg [0:0] Q; +output reg [0:0] QN; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- +always @(posedge CK) begin + if(RST) begin + Q <= 1'b0; + QN <= 1'b1; + end else begin + Q <= D; + QN <= ~D; + end +end + +// ----- Internal logic should end here ----- +endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v new file mode 100644 index 000000000..c466740c6 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v @@ -0,0 +1,36 @@ +module DFFSRQ(SET, + RST, + CK, + D, + Q); +//----- GLOBAL PORTS ----- +input [0:0] SET; +//----- GLOBAL PORTS ----- +input [0:0] RST; +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output reg [0:0] Q; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- +always @(posedge CK) begin + if(RST) begin + Q <= 1'b0; + else if(SET) begin + Q <= 1'b1; + end else begin + Q <= D; + end +end + +// ----- Internal logic should end here ----- +endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/inv.v b/openfpga_flow/openfpga_cell_library/verilog/inv.v new file mode 100644 index 000000000..cb208248f --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/inv.v @@ -0,0 +1,29 @@ +// ----- Verilog module for INVTX1 ----- +module INVTX1(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + //assign out = (in === 1'bz)? $random : ~in; + assign out = ~in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in[0] => out[0]) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for INVTX1 ----- + From 94f858fcdeffc3f74dd3ca667ce961cd9b3e6a9e Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 21:27:01 -0500 Subject: [PATCH 03/18] merge for consideration; --- .../synthesizable_verilog/config/task.conf | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf new file mode 100644 index 000000000..abfad8e89 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From d040ba569c4914dc53bd89c0553c8d1c6783fb4b Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 21:29:34 -0500 Subject: [PATCH 04/18] merge for consideration; --- .../tasks/fpga_verilog/synthesizable_verilog/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf index abfad8e89..ff4eca8d2 100644 --- a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif From 853bf8af434a7be7942047e8392025e5ae2c383b Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 22:03:14 -0500 Subject: [PATCH 05/18] typos fixed; --- .../k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml | 2 +- openfpga_flow/openfpga_cell_library/verilog/dffsrq.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml index 6d7b080f1..50c2769ad 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml @@ -40,7 +40,7 @@ 10e-12 - + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v index c466740c6..cff8848a9 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v @@ -25,7 +25,7 @@ output reg [0:0] Q; always @(posedge CK) begin if(RST) begin Q <= 1'b0; - else if(SET) begin + end else if(SET) begin Q <= 1'b1; end else begin Q <= D; From 45437fbc46434c4606282c846744cdcc82194bf6 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 22:27:57 -0500 Subject: [PATCH 06/18] no need for dff*, but need tap_buf4 --- ...tdcell_mux_40nm_openfpga_synthesizable.xml | 6 ++-- .../openfpga_cell_library/verilog/dffr.v | 35 ------------------ .../openfpga_cell_library/verilog/dffsrq.v | 36 ------------------- .../openfpga_cell_library/verilog/tap_buf4.v | 28 +++++++++++++++ 4 files changed, 31 insertions(+), 74 deletions(-) delete mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffr.v delete mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffsrq.v create mode 100644 openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml index 50c2769ad..95ccc9e2d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml @@ -52,7 +52,7 @@ 10e-12 - + @@ -131,7 +131,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffr.v b/openfpga_flow/openfpga_cell_library/verilog/dffr.v deleted file mode 100644 index 051fa71fb..000000000 --- a/openfpga_flow/openfpga_cell_library/verilog/dffr.v +++ /dev/null @@ -1,35 +0,0 @@ -module DFFR(RST, - CK, - D, - Q, - QN); -//----- GLOBAL PORTS ----- -input [0:0] RST; -//----- GLOBAL PORTS ----- -input [0:0] CK; -//----- INPUT PORTS ----- -input [0:0] D; -//----- OUTPUT PORTS ----- -output reg [0:0] Q; -output reg [0:0] QN; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - -// ----- Internal logic should start here ----- -always @(posedge CK) begin - if(RST) begin - Q <= 1'b0; - QN <= 1'b1; - end else begin - Q <= D; - QN <= ~D; - end -end - -// ----- Internal logic should end here ----- -endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v deleted file mode 100644 index cff8848a9..000000000 --- a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v +++ /dev/null @@ -1,36 +0,0 @@ -module DFFSRQ(SET, - RST, - CK, - D, - Q); -//----- GLOBAL PORTS ----- -input [0:0] SET; -//----- GLOBAL PORTS ----- -input [0:0] RST; -//----- GLOBAL PORTS ----- -input [0:0] CK; -//----- INPUT PORTS ----- -input [0:0] D; -//----- OUTPUT PORTS ----- -output reg [0:0] Q; - -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - -// ----- Internal logic should start here ----- -always @(posedge CK) begin - if(RST) begin - Q <= 1'b0; - end else if(SET) begin - Q <= 1'b1; - end else begin - Q <= D; - end -end - -// ----- Internal logic should end here ----- -endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v b/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v new file mode 100644 index 000000000..cb0be94c5 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v @@ -0,0 +1,28 @@ +// ----- Verilog module for tap_buf4 ----- +module tap_buf4(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + //assign out = (in === 1'bz)? $random : ~in; + assign out = ~in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in[0] => out[0]) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for tap_buf4 ----- From e14c0bf0c4309092ca1659705ade24a29e1fd08f Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 22:28:42 -0500 Subject: [PATCH 07/18] no need for dff*, but need tap_buf4 --- openfpga_flow/openfpga_cell_library/verilog/buf4.v | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openfpga_flow/openfpga_cell_library/verilog/buf4.v b/openfpga_flow/openfpga_cell_library/verilog/buf4.v index a9f0585bc..656d7b806 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/buf4.v +++ b/openfpga_flow/openfpga_cell_library/verilog/buf4.v @@ -1,3 +1,9 @@ +// ----- Verilog module for const0 ----- +module const0(const0); +output [0:0] const0; +assign const0[0] = 1'b0; +endmodule + // ----- Verilog module for buf4 ----- module buf4(in, out); From cf154d8bb943935379906e9effda9180112b49ea Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 22:29:55 -0500 Subject: [PATCH 08/18] no need for dff*, but need tap_buf4 --- openfpga_flow/openfpga_cell_library/verilog/buf4.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openfpga_flow/openfpga_cell_library/verilog/buf4.v b/openfpga_flow/openfpga_cell_library/verilog/buf4.v index 656d7b806..aadf7e5b5 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/buf4.v +++ b/openfpga_flow/openfpga_cell_library/verilog/buf4.v @@ -4,6 +4,13 @@ output [0:0] const0; assign const0[0] = 1'b0; endmodule +// ----- Verilog module for const0 ----- +module const1(const1); +output [0:0] const1; +assign const1[0] = 1'b1; +endmodule + + // ----- Verilog module for buf4 ----- module buf4(in, out); From 485708423c06991d06e765fb77e682f2623a1f46 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 23:00:13 -0500 Subject: [PATCH 09/18] no need for dff*, but need tap_buf4 --- ...tdcell_mux_40nm_openfpga_synthesizable.xml | 4 +-- .../openfpga_cell_library/verilog/or2.v | 31 +++++++++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/openfpga_cell_library/verilog/or2.v diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml index 95ccc9e2d..0f09f9d23 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml @@ -52,7 +52,7 @@ 10e-12 - @@ -64,7 +64,7 @@ 10e-12 - + diff --git a/openfpga_flow/openfpga_cell_library/verilog/or2.v b/openfpga_flow/openfpga_cell_library/verilog/or2.v new file mode 100644 index 000000000..ec93d17f8 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/or2.v @@ -0,0 +1,31 @@ +// ----- Verilog module for OR2 ----- +module OR2(a, + b, + out); +//----- INPUT PORTS ----- +input [0:0] a; +//----- INPUT PORTS ----- +input [0:0] b; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a 2-input 1-output AND gate ----- + assign out[0] = a[0] | b[0]; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (a[0] => out[0]) = (0.01, 0.01); + (b[0] => out[0]) = (0.005, 0.005); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for OR2 ----- From d7967da32807f8174c7e0e71ef28891da4bc72e4 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 23:04:00 -0500 Subject: [PATCH 10/18] bugfix in alt --- openfpga_flow/openfpga_cell_library/verilog/buf4.v | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/buf4.v b/openfpga_flow/openfpga_cell_library/verilog/buf4.v index aadf7e5b5..a9f0585bc 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/buf4.v +++ b/openfpga_flow/openfpga_cell_library/verilog/buf4.v @@ -1,16 +1,3 @@ -// ----- Verilog module for const0 ----- -module const0(const0); -output [0:0] const0; -assign const0[0] = 1'b0; -endmodule - -// ----- Verilog module for const0 ----- -module const1(const1); -output [0:0] const1; -assign const1[0] = 1'b1; -endmodule - - // ----- Verilog module for buf4 ----- module buf4(in, out); From b14b5f975da25b11d6d6f0c631d7c85e929e0451 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 08:48:25 -0500 Subject: [PATCH 11/18] adding sweep for W --- .../synthesizable_verilog/config/task.conf | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf index ff4eca8d2..197bef1c8 100644 --- a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf @@ -34,3 +34,27 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= + +[SCRIPT_PARAM_Fixed_Routing_30] +fix_route_chan_width=30 + +[SCRIPT_PARAM_Fixed_Routing_40] +fix_route_chan_width=40 + +[SCRIPT_PARAM_Fixed_Routing_50] +fix_route_chan_width=50 + +[SCRIPT_PARAM_Fixed_Routing_60] +fix_route_chan_width=60 + +[SCRIPT_PARAM_Fixed_Routing_70] +fix_route_chan_width=70 + +[SCRIPT_PARAM_Fixed_Routing_80] +fix_route_chan_width=80 + +[SCRIPT_PARAM_Fixed_Routing_90] +fix_route_chan_width=90 + +[SCRIPT_PARAM_Fixed_Routing_100] +fix_route_chan_width=100 From 95fe4d7dae866f98038edbc8c862449293e46bfe Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 10:34:54 -0500 Subject: [PATCH 12/18] adding dff synth --- .../openfpga_cell_library/verilog/dffsynth.v | 360 ++++++++++++++++++ .../openfpga_cell_library/verilog/inv.v | 26 +- 2 files changed, 363 insertions(+), 23 deletions(-) create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffsynth.v diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v b/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v new file mode 100644 index 000000000..c97da167b --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v @@ -0,0 +1,360 @@ +//----------------------------------------------------- +// Design Name : D-type Flip-flops +// File Name : ff.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A native D-type flip-flop with single output +//----------------------------------------------------- +module DFFQ ( + input CK, // Clock Input + input D, // Data Input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (posedge CK) begin + q_reg <= D; +end + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : A native D-type flip-flop +//----------------------------------------------------- +module DFF ( + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (posedge CK) begin + q_reg <= D; +end + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - single output +// - asynchronous active high reset +//----------------------------------------------------- +module DFFRQ ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +//----------------------------------------------------- +module DFFR ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low reset +//----------------------------------------------------- +module DFFRN ( + input RSTN, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge RSTN) +if (~RSTN) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high set +//----------------------------------------------------- +module DFFS ( + input SET, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge SET) +if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low set +//----------------------------------------------------- +module DFFSN ( + input SETN, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge SETN) +if (~SETN) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSR ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSRQ ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +assign Q = q_reg; + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSR ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFRQ ( + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +assign Q = q_reg; + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSRQ ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +assign Q = q_reg; + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - scan-chain input +// - a scan-chain enable +// - a configure enable, when enabled the registered output will +// be released to the Q +//----------------------------------------------------- +module CFGSDFFR ( + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + input CFGE, // Configure enable + output Q, // Regular Q output + output CFGQ, // Data Q output which is released when configure enable is activated + output CFGQN // Data Qb output which is released when configure enable is activated +); +//------------Internal Variables-------- +reg q_reg; +wire QN; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +assign CFGQ = CFGE ? Q : 1'b0; +assign CFGQN = CFGE ? QN : 1'b1; + +endmodule //End Of Module diff --git a/openfpga_flow/openfpga_cell_library/verilog/inv.v b/openfpga_flow/openfpga_cell_library/verilog/inv.v index cb208248f..f62e59f33 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/inv.v +++ b/openfpga_flow/openfpga_cell_library/verilog/inv.v @@ -1,29 +1,9 @@ // ----- Verilog module for INVTX1 ----- -module INVTX1(in, - out); -//----- INPUT PORTS ----- -input [0:0] in; -//----- OUTPUT PORTS ----- -output [0:0] out; +module INVTX1(in, out); + input [0:0] in; + output [0:0] out; -//----- BEGIN wire-connection ports ----- -//----- END wire-connection ports ----- - - -//----- BEGIN Registered ports ----- -//----- END Registered ports ----- - -// ----- Verilog codes of a regular inverter ----- - //assign out = (in === 1'bz)? $random : ~in; assign out = ~in; -`ifdef ENABLE_TIMING -// ------ BEGIN Pin-to-pin Timing constraints ----- - specify - (in[0] => out[0]) = (0.01, 0.01); - endspecify -// ------ END Pin-to-pin Timing constraints ----- -`endif endmodule -// ----- END Verilog module for INVTX1 ----- From cc74c6268a3eef065ed5ec1e34fbf9b8e16be398 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 11:28:19 -0500 Subject: [PATCH 13/18] trying fix chan width --- .../openfpga_cell_library/verilog/dffsynth.v | 360 ------------------ .../synthesizable_verilog/config/task.conf | 27 +- 2 files changed, 3 insertions(+), 384 deletions(-) delete mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffsynth.v diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v b/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v deleted file mode 100644 index c97da167b..000000000 --- a/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v +++ /dev/null @@ -1,360 +0,0 @@ -//----------------------------------------------------- -// Design Name : D-type Flip-flops -// File Name : ff.v -// Coder : Xifan TANG -//----------------------------------------------------- - -//----------------------------------------------------- -// Function : A native D-type flip-flop with single output -//----------------------------------------------------- -module DFFQ ( - input CK, // Clock Input - input D, // Data Input - output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (posedge CK) begin - q_reg <= D; -end - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : A native D-type flip-flop -//----------------------------------------------------- -module DFF ( - input CK, // Clock Input - input D, // Data Input - output Q, // Q output - output QN // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (posedge CK) begin - q_reg <= D; -end - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - single output -// - asynchronous active high reset -//----------------------------------------------------- -module DFFRQ ( - input RST, // Reset input - input CK, // Clock Input - input D, // Data Input - output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST) -if (RST) begin - q_reg <= 1'b0; -end else begin - q_reg <= D; -end - -endmodule //End Of Module - - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high reset -//----------------------------------------------------- -module DFFR ( - input RST, // Reset input - input CK, // Clock Input - input D, // Data Input - output Q, // Q output - output QN // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST) -if (RST) begin - q_reg <= 1'b0; -end else begin - q_reg <= D; -end - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active low reset -//----------------------------------------------------- -module DFFRN ( - input RSTN, // Reset input - input CK, // Clock Input - input D, // Data Input - output Q, // Q output - output QN // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or negedge RSTN) -if (~RSTN) begin - q_reg <= 1'b0; -end else begin - q_reg <= D; -end - -endmodule //End Of Module - - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high set -//----------------------------------------------------- -module DFFS ( - input SET, // Set input - input CK, // Clock Input - input D, // Data Input - output Q, // Q output - output QN // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge SET) -if (SET) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active low set -//----------------------------------------------------- -module DFFSN ( - input SETN, // Set input - input CK, // Clock Input - input D, // Data Input - output Q, // Q output - output QN // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or negedge SETN) -if (~SETN) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -endmodule //End Of Module - - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high reset -// - asynchronous active high set -//----------------------------------------------------- -module DFFSR ( - input SET, // set input - input RST, // Reset input - input CK, // Clock Input - input D, // Data Input - output Q, // Q output - output QN // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST or posedge SET) -if (RST) begin - q_reg <= 1'b0; -end else if (SET) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high reset -// - asynchronous active high set -//----------------------------------------------------- -module DFFSRQ ( - input SET, // set input - input RST, // Reset input - input CK, // Clock Input - input D, // Data Input - output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST or posedge SET) -if (RST) begin - q_reg <= 1'b0; -end else if (SET) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -assign Q = q_reg; - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high reset -// - asynchronous active high set -// - scan-chain input -// - a scan-chain enable -//----------------------------------------------------- -module SDFFSR ( - input SET, // Set input - input RST, // Reset input - input CK, // Clock Input - input SE, // Scan-chain Enable - input D, // Data Input - input SI, // Scan-chain input - output Q, // Q output - output QN // Q negative output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST or posedge SET) -if (RST) begin - q_reg <= 1'b0; -end else if (SET) begin - q_reg <= 1'b1; -end else if (SE) begin - q_reg <= SI; -end else begin - q_reg <= D; -end - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high reset -// - scan-chain input -// - a scan-chain enable -//----------------------------------------------------- -module SDFFRQ ( - input RST, // Reset input - input CK, // Clock Input - input SE, // Scan-chain Enable - input D, // Data Input - input SI, // Scan-chain input - output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST) -if (RST) begin - q_reg <= 1'b0; -end else if (SE) begin - q_reg <= SI; -end else begin - q_reg <= D; -end - -assign Q = q_reg; - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high reset -// - asynchronous active high set -// - scan-chain input -// - a scan-chain enable -//----------------------------------------------------- -module SDFFSRQ ( - input SET, // Set input - input RST, // Reset input - input CK, // Clock Input - input SE, // Scan-chain Enable - input D, // Data Input - input SI, // Scan-chain input - output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST or posedge SET) -if (RST) begin - q_reg <= 1'b0; -end else if (SET) begin - q_reg <= 1'b1; -end else if (SE) begin - q_reg <= SI; -end else begin - q_reg <= D; -end - -assign Q = q_reg; - -endmodule //End Of Module - -//----------------------------------------------------- -// Function : D-type flip-flop with -// - asynchronous active high reset -// - scan-chain input -// - a scan-chain enable -// - a configure enable, when enabled the registered output will -// be released to the Q -//----------------------------------------------------- -module CFGSDFFR ( - input RST, // Reset input - input CK, // Clock Input - input SE, // Scan-chain Enable - input D, // Data Input - input SI, // Scan-chain input - input CFGE, // Configure enable - output Q, // Regular Q output - output CFGQ, // Data Q output which is released when configure enable is activated - output CFGQN // Data Qb output which is released when configure enable is activated -); -//------------Internal Variables-------- -reg q_reg; -wire QN; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST) -if (RST) begin - q_reg <= 1'b0; -end else if (SE) begin - q_reg <= SI; -end else begin - q_reg <= D; -end - -assign CFGQ = CFGE ? Q : 1'b0; -assign CFGQN = CFGE ? QN : 1'b1; - -endmodule //End Of Module diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf index 197bef1c8..6d11cacf5 100644 --- a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf @@ -16,9 +16,12 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] +#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +#openfpga_vpr_device_layout=2x2 +#openfpga_vpr_route_chan_width=10 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml @@ -34,27 +37,3 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= - -[SCRIPT_PARAM_Fixed_Routing_30] -fix_route_chan_width=30 - -[SCRIPT_PARAM_Fixed_Routing_40] -fix_route_chan_width=40 - -[SCRIPT_PARAM_Fixed_Routing_50] -fix_route_chan_width=50 - -[SCRIPT_PARAM_Fixed_Routing_60] -fix_route_chan_width=60 - -[SCRIPT_PARAM_Fixed_Routing_70] -fix_route_chan_width=70 - -[SCRIPT_PARAM_Fixed_Routing_80] -fix_route_chan_width=80 - -[SCRIPT_PARAM_Fixed_Routing_90] -fix_route_chan_width=90 - -[SCRIPT_PARAM_Fixed_Routing_100] -fix_route_chan_width=100 From 87c69460dfcd4c046384e93184b84983c3a4be3a Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 11:33:08 -0500 Subject: [PATCH 14/18] what is going on --- .../fpga_verilog/synthesizable_verilog/config/task.conf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf index 6d11cacf5..ea7fb490d 100644 --- a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf @@ -16,12 +16,12 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -#openfpga_vpr_device_layout=2x2 -#openfpga_vpr_route_chan_width=10 +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=10 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml From 6bb2e29f17f1c62fe2e0c1dd5199697aabccbd33 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 17:04:52 -0500 Subject: [PATCH 15/18] default to ns for time unit -- synopsys dc whines --- .../fix_device_route_chan_width_example_script.openfpga | 2 +- .../tasks/fpga_verilog/synthesizable_verilog/config/task.conf | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index c03f2b175..670aabf2c 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -59,7 +59,7 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # Write the SDC files for PnR backend # - Turn on every options here -write_pnr_sdc --file ./SDC +write_pnr_sdc --time-unit ns --file ./SDC # Write SDC to disable timing for configure ports write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf index ea7fb490d..22fe003b9 100644 --- a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf @@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip #openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=10 +openfpga_vpr_device_layout=auto +openfpga_vpr_route_chan_width=20 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml From 71c76df063f3100b3aa91a9027d403f368777e78 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 17:08:38 -0500 Subject: [PATCH 16/18] default to ns for time unit -- synopsys dc whines --- .../fix_device_route_chan_width_example_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index 670aabf2c..11e14faba 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -59,7 +59,7 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # Write the SDC files for PnR backend # - Turn on every options here -write_pnr_sdc --time-unit ns --file ./SDC +write_pnr_sdc --time_unit ns --flatten_names --file ./SDC # Write SDC to disable timing for configure ports write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc From 4c7f4bd82f8dda9353131f0d48492691d973a861 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 17:38:19 -0500 Subject: [PATCH 17/18] ahoy nice --- .../fix_device_route_chan_width_example_script.openfpga | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index 11e14faba..054f74c0e 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -60,6 +60,7 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # Write the SDC files for PnR backend # - Turn on every options here write_pnr_sdc --time_unit ns --flatten_names --file ./SDC +write_pnr_sdc --time_unit ns --flatten_names --hierarchical --file ./SDC_leaf # Write SDC to disable timing for configure ports write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc From 808df8a87e49376d866b70b14a82846fce70bf54 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 17 Feb 2021 13:23:45 -0700 Subject: [PATCH 18/18] [Bugfix] Docker regression using master regression scripts --- .github/workflows/build.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index d8e42b28b..4df847609 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -266,6 +266,7 @@ jobs: bash .github/workflows/install_dependencies_run.sh ${PYTHON_EXEC} -m pip install -r requirements.txt rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. . + unset OPENFPGA_PATH source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh - name: Upload artifact uses: actions/upload-artifact@v2