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[FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks

This commit is contained in:
tangxifan 2022-02-13 19:55:16 -08:00
parent 4703753807
commit a068237082
4 changed files with 28 additions and 6 deletions
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16
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -71,7 +71,7 @@ void print_verilog_preconfig_top_module_ports(std::fstream &fp,
fp << "," << std::endl;
}
/* Both input and output ports have only size of 1 */
BasicPort module_port(std::string(block_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)), 1);
BasicPort module_port(std::string(block_name), 1);
fp << generate_verilog_port(port_type2type_map[atom_ctx.nlist.block_type(atom_blk)], module_port);
/* Update port counter */
@ -100,6 +100,8 @@ void print_verilog_preconfig_top_module_internal_wires(std::fstream &fp,
print_verilog_comment(fp, std::string("----- Local wires for FPGA fabric -----"));
for (const ModulePortId &module_port_id : module_manager.module_ports(top_module)) {
BasicPort module_port = module_manager.module_port(top_module, module_port_id);
/* Add a postfix to the internal wires to be different from other reserved ports */
module_port.set_name(module_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
}
/* Add an empty line as a splitter */
@ -132,7 +134,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
&& (false == fabric_global_ports.global_port_is_prog(global_port_id))) {
/* Wiring to each pin of the global port: benchmark clock is always 1-bit */
for (size_t pin_id = 0; pin_id < module_global_port.pins().size(); ++pin_id) {
BasicPort module_clock_pin(module_global_port.get_name(), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]);
BasicPort module_clock_pin(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]);
/* If the clock port name is in the pin constraints, we should wire it to the constrained pin */
std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin);
@ -159,7 +161,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
clock_name_to_connect = benchmark_clock_port_names[pin_id];
}
BasicPort benchmark_clock_pin(clock_name_to_connect + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 1);
BasicPort benchmark_clock_pin(clock_name_to_connect, 1);
print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin, false);
}
/* Finish, go to the next */
@ -168,7 +170,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
/* For other ports, give an default value */
for (size_t pin_id = 0; pin_id < module_global_port.pins().size(); ++pin_id) {
BasicPort module_global_pin(module_global_port.get_name(),
BasicPort module_global_pin(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
module_global_port.pins()[pin_id],
module_global_port.pins()[pin_id]);
@ -180,7 +182,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
*/
if ( (false == pin_constraints.unconstrained_net(constrained_net_name))
&& (false == pin_constraints.unmapped_net(constrained_net_name))) {
BasicPort benchmark_pin(constrained_net_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 1);
BasicPort benchmark_pin(constrained_net_name, 1);
print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, false);
} else {
VTR_ASSERT_SAFE(std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name);
@ -454,6 +456,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
/* Instanciate FPGA top-level module */
print_verilog_testbench_fpga_instance(fp, module_manager, top_module,
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
options.explicit_port_mapping());
/* Find clock ports in benchmark */
@ -472,7 +475,8 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(),
std::string(),
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Assign the SRAM model applied to the FPGA fabric */

14
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -32,11 +32,16 @@ namespace openfpga {
/********************************************************************
* Print an instance of the FPGA top-level module
* When net_postfix is not empty, the instance net will contain a postfix like
* fpga fpga_core(.in(in_<postfix>),
.out(out_postfix>)
);
*******************************************************************/
void print_verilog_testbench_fpga_instance(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const std::string& top_instance_name,
const std::string& net_postfix,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -46,6 +51,12 @@ void print_verilog_testbench_fpga_instance(std::fstream& fp,
/* Create an empty port-to-port name mapping, because we use default names */
std::map<std::string, BasicPort> port2port_name_map;
if (!net_postfix.empty()) {
for (const ModulePortId &module_port_id : module_manager.module_ports(top_module)) {
BasicPort module_port = module_manager.module_port(top_module, module_port_id);
port2port_name_map[module_port.get_name()] = module_port.get_name() + net_postfix;
}
}
/* Use explicit port mapping for a clean instanciation */
print_verilog_module_instance(fp, module_manager, top_module,
@ -157,6 +168,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& net_name_postfix,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const size_t& unused_io_value) {
@ -242,6 +254,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
/* Set the port pin index */
VTR_ASSERT(io_index < module_mapped_io_port.get_width());
module_mapped_io_port.set_name(module_mapped_io_port.get_name() + net_name_postfix);
module_mapped_io_port.set_width(io_index, io_index);
/* The block may be renamed as it contains special characters which violate Verilog syntax */
@ -292,6 +305,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
/* Wire to a contant */
BasicPort module_unused_io_port = module_manager.module_port(top_module, module_io_port_id);
/* Set the port pin index */
module_unused_io_port.set_name(module_unused_io_port.get_name() + net_name_postfix);
module_unused_io_port.set_width(io_index, io_index);
std::vector<size_t> default_values(module_unused_io_port.get_width(), unused_io_value);

2
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -27,6 +27,7 @@ void print_verilog_testbench_fpga_instance(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const std::string& top_instance_name,
const std::string& net_postfix,
const bool& explicit_port_mapping);
void print_verilog_testbench_benchmark_instance(std::fstream& fp,
@ -48,6 +49,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const PlacementContext& place_ctx,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& net_name_postfix,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const size_t& unused_io_value);

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2042,6 +2042,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
/* Instanciate FPGA top-level module */
print_verilog_testbench_fpga_instance(fp, module_manager, top_module,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
std::string(),
explicit_port_mapping);
/* Connect I/Os to benchmark I/Os or constant driver */
@ -2049,6 +2050,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
std::string(),
std::string(),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);