From 9ff5e7926bd0b74453375b816c9e26b937824f54 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Feb 2021 09:24:39 -0700 Subject: [PATCH] [Test] Update test case to use the adder benchmark --- .../tasks/fpga_verilog/adder/soft_adder/config/task.conf | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 98c283a53..8a94c37ea 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -16,21 +16,22 @@ timeout_each_job = 1*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.blif [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]