From 9f4d05da67496dd13ceecfd4b43bdc206b07ef04 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 28 Feb 2021 16:11:30 -0700 Subject: [PATCH] [Test] Bug fix for new test case --- .../explicit_port_mapping_default_nettype_wire/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire/config/task.conf index 3dcbbe965..495c175dd 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_verilog_default_net_type=wire