From cc73771667c2779079b64933c0244097cd931790 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Aug 2023 10:34:57 -0700 Subject: [PATCH 1/6] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 0963c2047..5bea5da82 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 0963c20472e178d6562e40d90727870342035f67 +Subproject commit 5bea5da827600c06990be740b580213eebae6263 From 867da98d3f9281cac94c1b4a9b70a24b0a6755a0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Aug 2023 16:28:19 -0700 Subject: [PATCH 2/6] [core] update to use latest api from vpr upstream --- CMakeLists.txt | 4 +- openfpga/src/annotation/annotate_rr_graph.cpp | 33 +++++----- .../annotate_simulation_setting.cpp | 4 +- .../src/annotation/append_clock_rr_graph.cpp | 63 ++++++++++--------- .../annotation/openfpga_annotate_routing.cpp | 7 +-- .../annotation/vpr_placement_annotation.cpp | 2 +- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 23 ++++--- .../fabric/build_fabric_io_location_map.cpp | 22 ++++--- openfpga/src/fabric/build_fabric_tile.cpp | 14 +++-- .../src/fabric/build_routing_module_utils.cpp | 6 +- openfpga/src/fabric/build_tile_modules.cpp | 37 ++++++----- openfpga/src/fabric/build_top_module.cpp | 6 +- ...top_module_child_fine_grained_instance.cpp | 54 +++++++++------- ...d_top_module_child_fine_grained_instance.h | 1 + .../build_top_module_child_tile_instance.cpp | 40 +++++++----- .../build_top_module_child_tile_instance.h | 1 + .../fabric/build_top_module_connection.cpp | 44 ++++++++----- .../src/fabric/build_top_module_connection.h | 2 + .../src/fabric/build_top_module_directs.cpp | 14 +++-- .../src/fabric/build_top_module_directs.h | 1 + .../src/fabric/build_top_module_memory.cpp | 16 +++-- openfpga/src/fabric/build_top_module_memory.h | 1 + .../src/fabric/build_top_module_utils.cpp | 4 +- .../fpga_bitstream/build_device_bitstream.cpp | 2 +- .../fpga_bitstream/build_grid_bitstream.cpp | 25 ++++---- .../src/fpga_bitstream/build_grid_bitstream.h | 3 +- .../src/fpga_sdc/analysis_sdc_grid_writer.cpp | 9 +-- .../src/tile_direct/build_tile_direct.cpp | 45 +++++++------ .../utils/openfpga_physical_tile_utils.cpp | 4 +- openfpga/src/vpr_wrapper/vpr_main.cpp | 32 +++------- 30 files changed, 288 insertions(+), 231 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b21400b2f..100351184 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -109,9 +109,9 @@ endif() include(CheckCXXCompilerFlag) # -# We require c++14 support +# We require c++17 support # -set(CMAKE_CXX_STANDARD 14) +set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_STANDARD_REQUIRED ON) set(CMAKE_CXX_EXTENSIONS OFF) #No compiler specific extensions diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 84a994577..65cbbe01f 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -22,6 +22,7 @@ namespace openfpga { /* Build a RRChan Object with the given channel type and coorindators */ static RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx, const t_rr_type& chan_type, + const size_t& layer, vtr::Point& chan_coord) { std::vector chan_rr_nodes; @@ -32,7 +33,7 @@ static RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx, /* Collect rr_nodes for this channel */ chan_rr_nodes = find_rr_graph_chan_nodes( - vpr_device_ctx.rr_graph, chan_coord.x(), chan_coord.y(), chan_type); + vpr_device_ctx.rr_graph, layer, chan_coord.x(), chan_coord.y(), chan_type); /* Fill the rr_chan */ for (const RRNodeId& chan_rr_node : chan_rr_nodes) { rr_chan.add_node(vpr_device_ctx.rr_graph, chan_rr_node, @@ -96,6 +97,7 @@ static RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx, */ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_range, + const size_t& layer, const vtr::Point& gsb_coord, const bool& include_clock) { /* Create an object to return */ @@ -133,7 +135,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Routing channels*/ /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(vpr_device_ctx, CHANY, coordinate); + rr_chan = build_one_rr_chan(vpr_device_ctx, CHANY, layer, coordinate); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = @@ -147,11 +149,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, opin_grid_side[1] = LEFT; /* Include Grid[x][y+1] RIGHT side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x(), + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x(), gsb_coord.y() + 1, OPIN, opin_grid_side[0]); /* Include Grid[x+1][y+1] Left side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x() + 1, + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[1]); break; @@ -165,7 +167,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(vpr_device_ctx, CHANX, coordinate); + rr_chan = build_one_rr_chan(vpr_device_ctx, CHANX, layer, coordinate); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = @@ -180,11 +182,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* include Grid[x+1][y+1] Bottom side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x() + 1, + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[0]); /* include Grid[x+1][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x() + 1, + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ @@ -197,7 +199,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(vpr_device_ctx, CHANY, coordinate); + rr_chan = build_one_rr_chan(vpr_device_ctx, CHANY, layer, coordinate); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = @@ -211,11 +213,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, opin_grid_side[1] = RIGHT; /* include Grid[x+1][y] Left side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x() + 1, + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[0]); /* include Grid[x][y] Right side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x(), + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x(), gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ @@ -228,7 +230,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for left: chanx[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(vpr_device_ctx, CHANX, coordinate); + rr_chan = build_one_rr_chan(vpr_device_ctx, CHANX, layer, coordinate); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = @@ -241,11 +243,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, opin_grid_side[1] = TOP; /* include Grid[x][y+1] Bottom side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x(), + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x(), gsb_coord.y() + 1, OPIN, opin_grid_side[0]); /* include Grid[x][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, gsb_coord.x(), + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x(), gsb_coord.y(), OPIN, opin_grid_side[1]); break; default: @@ -370,7 +372,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, } /* Collect IPIN rr_nodes*/ temp_ipin_rr_nodes = - find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, ix, + find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, ix, iy, IPIN, ipin_rr_node_grid_side, include_clock); /* Fill the ipin nodes of RRGSB */ for (const RRNodeId& inode : temp_ipin_rr_nodes) { @@ -422,6 +424,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_range.x(), gsb_range.y()); size_t gsb_cnt = 0; + size_t layer = 0; /* For each switch block, determine the size of array */ for (size_t ix = 0; ix < gsb_range.x(); ++ix) { for (size_t iy = 0; iy < gsb_range.y(); ++iy) { @@ -433,7 +436,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, build_rr_gsb(vpr_device_ctx, vtr::Point(vpr_device_ctx.grid.width() - 2, vpr_device_ctx.grid.height() - 2), - vtr::Point(ix, iy), include_clock); + layer, vtr::Point(ix, iy), include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); diff --git a/openfpga/src/annotation/annotate_simulation_setting.cpp b/openfpga/src/annotation/annotate_simulation_setting.cpp index 3c3c7b3ee..8f4014427 100644 --- a/openfpga/src/annotation/annotate_simulation_setting.cpp +++ b/openfpga/src/annotation/annotate_simulation_setting.cpp @@ -16,7 +16,7 @@ #include "AnalysisDelayCalculator.h" #include "annotate_simulation_setting.h" #include "net_delay.h" -#include "timing_info.h" +#include "concrete_timing_info.h" /* begin namespace openfpga */ namespace openfpga { @@ -212,7 +212,7 @@ int annotate_simulation_setting( make_net_pins_matrix((const Netlist<>&)cluster_ctx.clb_nlist); /* Load the net delays */ load_net_delay_from_routing((const Netlist<>&)cluster_ctx.clb_nlist, - net_delay, false); + net_delay); /* Do final timing analysis */ auto analysis_delay_calc = std::make_shared( diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 96fe420b3..0f9e1ecbd 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -44,6 +44,7 @@ static size_t estimate_clock_rr_graph_num_chan_nodes( * Note that switch blocks do not require any new nodes but new edges *******************************************************************/ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, + const size_t& layer, const bool& through_channel, const ClockNetwork& clk_ntwk) { size_t num_nodes = 0; @@ -54,7 +55,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -68,7 +69,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -87,11 +88,12 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, static void add_rr_graph_block_clock_nodes( RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const ClockNetwork& clk_ntwk, + const size_t& layer, const vtr::Point chan_coord, const t_rr_type& chan_type, const int& cost_index_offset, const bool& verbose) { size_t orig_chan_width = rr_graph_view.node_lookup() - .find_channel_nodes(chan_coord.x(), chan_coord.y(), chan_type) + .find_channel_nodes(layer, chan_coord.x(), chan_coord.y(), chan_type) .size(); size_t curr_node_ptc = orig_chan_width; @@ -115,9 +117,10 @@ static void add_rr_graph_block_clock_nodes( for (size_t ipin = 0; ipin < num_pins / 2; ++ipin) { for (auto node_dir : {Direction::INC, Direction::DEC}) { RRNodeId clk_node = rr_graph_builder.create_node( - chan_coord.x(), chan_coord.y(), chan_type, curr_node_ptc); + layer, chan_coord.x(), chan_coord.y(), chan_type, curr_node_ptc); rr_graph_builder.set_node_direction(clk_node, node_dir); rr_graph_builder.set_node_capacity(clk_node, 1); + rr_graph_builder.set_node_layer(clk_node, layer); /* set cost_index using segment id */ rr_graph_builder.set_node_cost_index( clk_node, RRIndexedDataId(cost_index_offset + @@ -149,6 +152,7 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const DeviceGrid& grids, + const size_t& layer, const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { @@ -164,11 +168,11 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } add_rr_graph_block_clock_nodes(rr_graph_builder, clk_rr_lookup, - rr_graph_view, clk_ntwk, chanx_coord, + rr_graph_view, clk_ntwk, layer, chanx_coord, CHANX, CHANX_COST_INDEX_START, verbose); VTR_ASSERT(rr_graph_view.valid_node( clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), @@ -186,11 +190,11 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord))) { continue; } add_rr_graph_block_clock_nodes( - rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, chany_coord, + rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chany_coord, CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose); VTR_ASSERT(rr_graph_view.valid_node( @@ -392,11 +396,12 @@ static std::vector find_clock_track2track_node( *******************************************************************/ static void try_find_and_add_clock_track2ipin_node( std::vector& des_nodes, const DeviceGrid& grids, - const RRGraphView& rr_graph_view, const vtr::Point& grid_coord, + const RRGraphView& rr_graph_view, const size_t& layer, + const vtr::Point& grid_coord, const e_side& pin_side, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) { t_physical_tile_type_ptr grid_type = - grids.get_physical_type(grid_coord.x(), grid_coord.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) { /* tap pin name could be 'io[5:5].a2f[0]' */ @@ -405,7 +410,7 @@ static void try_find_and_add_clock_track2ipin_node( continue; } RRNodeId des_node = rr_graph_view.node_lookup().find_node( - grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); + layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { des_nodes.push_back(des_node); } @@ -440,7 +445,7 @@ static void try_find_and_add_clock_track2ipin_node( *******************************************************************/ static std::vector find_clock_track2ipin_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, - const t_rr_type& chan_type, const vtr::Point& chan_coord, + const t_rr_type& chan_type, const size_t& layer, const vtr::Point& chan_coord, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) { std::vector des_nodes; @@ -449,26 +454,26 @@ static std::vector find_clock_track2ipin_node( /* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */ vtr::Point bot_grid_coord(chan_coord.x(), chan_coord.y() + 1); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - bot_grid_coord, BOTTOM, clk_ntwk, + layer, bot_grid_coord, BOTTOM, clk_ntwk, clk_tree, clk_pin); /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */ vtr::Point top_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - top_grid_coord, TOP, clk_ntwk, + layer, top_grid_coord, TOP, clk_ntwk, clk_tree, clk_pin); } else { VTR_ASSERT(chan_type == CHANY); /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */ vtr::Point left_grid_coord(chan_coord.x() + 1, chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - left_grid_coord, LEFT, clk_ntwk, + layer, left_grid_coord, LEFT, clk_ntwk, clk_tree, clk_pin); /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */ vtr::Point right_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - right_grid_coord, RIGHT, clk_ntwk, + layer, right_grid_coord, RIGHT, clk_ntwk, clk_tree, clk_pin); } @@ -481,7 +486,9 @@ static std::vector find_clock_track2ipin_node( static void add_rr_graph_block_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const ClockNetwork& clk_ntwk, + const DeviceGrid& grids, + const size_t& layer, + const ClockNetwork& clk_ntwk, const vtr::Point& chan_coord, const t_rr_type& chan_type, const bool& verbose) { size_t edge_count = 0; @@ -524,7 +531,7 @@ static void add_rr_graph_block_clock_edges( /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_switch()); + clk_ntwk.default_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", @@ -535,12 +542,12 @@ static void add_rr_graph_block_clock_edges( if (clk_ntwk.is_last_level(itree, ilvl)) { size_t curr_edge_count = edge_count; for (RRNodeId des_node : find_clock_track2ipin_node( - grids, rr_graph_view, chan_type, chan_coord, clk_ntwk, itree, + grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk, itree, ClockTreePinId(ipin))) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_switch()); + clk_ntwk.default_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", @@ -579,7 +586,7 @@ static void add_rr_graph_block_clock_edges( static void add_rr_graph_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const bool& through_channel, + const DeviceGrid& grids, const size_t& layer, const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Add edges which is driven by X-direction clock routing tracks */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { @@ -588,11 +595,11 @@ static void add_rr_graph_clock_edges( /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, - clk_rr_lookup, rr_graph_view, grids, + clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, chanx_coord, CHANX, verbose); } } @@ -604,11 +611,11 @@ static void add_rr_graph_clock_edges( /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, - clk_rr_lookup, rr_graph_view, grids, + clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, chany_coord, CHANY, verbose); } } @@ -647,7 +654,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes( - vpr_device_ctx.grid, vpr_device_ctx.arch->through_channel, clk_ntwk); + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->through_channel, clk_ntwk); vpr_device_ctx.rr_graph_builder.unlock_storage(); vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes + orig_num_nodes); @@ -658,7 +665,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Add clock nodes */ add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, @@ -673,7 +680,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, add_rr_graph_clock_edges( vpr_device_ctx.rr_graph_builder, num_clock_edges, static_cast(clk_rr_lookup), - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock edges to routing " diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 6c5327e04..e4aa8e88d 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -2,9 +2,8 @@ * This file includes functions that are used to annotate routing results * from VPR to OpenFPGA *******************************************************************/ -/* Headers from vtrutil library */ #include "openfpga_annotate_routing.h" - +#include "old_traceback.h" #include "annotate_routing.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -134,13 +133,13 @@ void annotate_rr_node_previous_nodes( /* Cache Previous nodes */ RRNodeId prev_node = RRNodeId::INVALID(); - t_trace* tptr = routing_ctx.trace[net_id].head; + t_trace* tptr = TracebackCompat::traceback_from_route_tree(routing_ctx.route_trees[net_id].value()); while (tptr != nullptr) { RRNodeId rr_node = RRNodeId(tptr->index); /* Find the right previous node */ prev_node = find_previous_node_from_routing_traces( - device_ctx.rr_graph, routing_ctx.trace[net_id].head, prev_node, + device_ctx.rr_graph, TracebackCompat::traceback_from_route_tree(routing_ctx.route_trees[net_id].value()), prev_node, rr_node); /* Only update mapped nodes */ diff --git a/openfpga/src/annotation/vpr_placement_annotation.cpp b/openfpga/src/annotation/vpr_placement_annotation.cpp index efdcb0ea6..0f24b05fd 100644 --- a/openfpga/src/annotation/vpr_placement_annotation.cpp +++ b/openfpga/src/annotation/vpr_placement_annotation.cpp @@ -32,7 +32,7 @@ void VprPlacementAnnotation::init_mapped_blocks(const DeviceGrid& grids) { for (size_t x = 0; x < grids.width(); ++x) { for (size_t y = 0; y < grids.height(); ++y) { /* Deposit invalid ids and we will fill later */ - blocks_[x][y].resize(grids.get_physical_type(x, y)->capacity, + blocks_[x][y].resize(grids.get_physical_type(t_physical_tile_loc(x, y, 0))->capacity, ClusterBlockId::INVALID()); } } diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 952a495d1..b57616f78 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -35,12 +35,13 @@ static void update_cluster_pin_with_post_routing_results( const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const VprRoutingAnnotation& vpr_routing_annotation, VprClusteringAnnotation& vpr_clustering_annotation, + const size_t& layer, const vtr::Point& grid_coord, const ClusterBlockId& blk_id, const e_side& border_side, const size_t& z, const bool& verbose) { /* Handle each pin */ auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id); auto physical_tile = - device_ctx.grid.get_physical_type(grid_coord.x(), grid_coord.y()); + device_ctx.grid.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (int j = 0; j < logical_block->pb_type->num_pins; j++) { /* Get the ptc num for the pin in rr_graph, we need t consider the z offset @@ -86,7 +87,7 @@ static void update_cluster_pin_with_post_routing_results( /* Find the net mapped to this pin in routing results */ const RRNodeId& rr_node = device_ctx.rr_graph.node_lookup().find_node( - grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side); + layer, grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side); if (false == device_ctx.rr_graph.valid_node(rr_node)) { continue; } @@ -192,16 +193,18 @@ void update_pb_pin_with_post_routing_results( * post-routing clustering result sync-up */ vpr_clustering_annotation.clear_net_remapping(); + size_t layer = 0; /* Update the core logic (center blocks of the FPGA) */ for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) { for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) { + t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type(t_physical_tile_loc(x, y, layer)); /* Bypass the EMPTY tiles */ - if (true == is_empty_type(device_ctx.grid.get_physical_type(x, y))) { + if (true == is_empty_type(phy_tile)) { continue; } /* Get the mapped blocks to this grid */ - for (const ClusterBlockId& cluster_blk_id : - placement_ctx.grid_blocks[x][y].blocks) { + for (int isubtile = 0; isubtile < phy_tile->capacity; ++isubtile) { + ClusterBlockId cluster_blk_id = placement_ctx.grid_blocks.block_at_location({(int)x, (int)y, (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { continue; @@ -211,7 +214,7 @@ void update_pb_pin_with_post_routing_results( vtr::Point grid_coord(x, y); update_cluster_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, - vpr_clustering_annotation, grid_coord, cluster_blk_id, NUM_SIDES, + vpr_clustering_annotation, layer, grid_coord, cluster_blk_id, NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, verbose); } } @@ -224,14 +227,14 @@ void update_pb_pin_with_post_routing_results( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coord : io_coordinates[io_side]) { t_physical_tile_type_ptr phy_tile_type = - device_ctx.grid.get_physical_type(io_coord.x(), io_coord.y()); + device_ctx.grid.get_physical_type(t_physical_tile_loc(io_coord.x(), io_coord.y(), layer)); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { continue; } /* Get the mapped blocks to this grid */ - for (const ClusterBlockId& cluster_blk_id : - placement_ctx.grid_blocks[io_coord.x()][io_coord.y()].blocks) { + for (int isubtile = 0; isubtile < phy_tile_type->capacity; ++isubtile) { + ClusterBlockId cluster_blk_id = placement_ctx.grid_blocks.block_at_location({(int)io_coord.x(), (int)io_coord.y(), (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { continue; @@ -239,7 +242,7 @@ void update_pb_pin_with_post_routing_results( /* Update on I/O grid */ update_cluster_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, - vpr_clustering_annotation, io_coord, cluster_blk_id, io_side, + vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, verbose); } } diff --git a/openfpga/src/fabric/build_fabric_io_location_map.cpp b/openfpga/src/fabric/build_fabric_io_location_map.cpp index c1f31f999..75b8d37ed 100644 --- a/openfpga/src/fabric/build_fabric_io_location_map.cpp +++ b/openfpga/src/fabric/build_fabric_io_location_map.cpp @@ -32,7 +32,7 @@ namespace openfpga { *(x, y, z) coordinate to the actual indices *******************************************************************/ static IoLocationMap build_fabric_fine_grained_io_location_map( - const ModuleManager& module_manager, const DeviceGrid& grids) { + const ModuleManager& module_manager, const DeviceGrid& grids, const size_t& layer) { vtr::ScopedStartFinishTimer timer( "Create I/O location mapping for top module"); @@ -50,8 +50,9 @@ static IoLocationMap build_fabric_fine_grained_io_location_map( ModuleId child = module_manager.io_children(top_module)[ichild]; vtr::Point coord = module_manager.io_child_coordinates(top_module)[ichild]; + t_physical_tile_loc phy_tile_loc(coord.x(), coord.y(), layer); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(coord.x(), coord.y()); + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { @@ -59,8 +60,8 @@ static IoLocationMap build_fabric_fine_grained_io_location_map( } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(coord.x(), coord.y())) || - (0 < grids.get_height_offset(coord.x(), coord.y()))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } @@ -153,7 +154,7 @@ static IoLocationMap build_fabric_fine_grained_io_location_map( *(x, y, z) coordinate to the actual indices *******************************************************************/ static IoLocationMap build_fabric_tiled_io_location_map( - const ModuleManager& module_manager, const DeviceGrid& grids) { + const ModuleManager& module_manager, const DeviceGrid& grids, const size_t& layer) { vtr::ScopedStartFinishTimer timer( "Create I/O location mapping for top module"); @@ -171,8 +172,9 @@ static IoLocationMap build_fabric_tiled_io_location_map( ModuleId child = module_manager.io_children(top_module)[ichild]; vtr::Point coord = module_manager.io_child_coordinates(top_module)[ichild]; + t_physical_tile_loc phy_tile_loc(coord.x(), coord.y(), layer); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(coord.x(), coord.y()); + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { @@ -180,8 +182,8 @@ static IoLocationMap build_fabric_tiled_io_location_map( } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(coord.x(), coord.y())) || - (0 < grids.get_height_offset(coord.x(), coord.y()))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } @@ -280,9 +282,9 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager, const DeviceGrid& grids, const bool& tiled_fabric) { if (tiled_fabric) { - return build_fabric_tiled_io_location_map(module_manager, grids); + return build_fabric_tiled_io_location_map(module_manager, grids, 0); } - return build_fabric_fine_grained_io_location_map(module_manager, grids); + return build_fabric_fine_grained_io_location_map(module_manager, grids, 0); } } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index c2dd79648..b1cc7c80e 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -29,6 +29,7 @@ namespace openfpga { *******************************************************************/ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, const DeviceGrid& grids, + const size_t& layer, const DeviceRRGSB& device_rr_gsb, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; @@ -36,7 +37,8 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, /* Walk through all the device rr_gsb and create tile one by one */ for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(ix, iy); + t_physical_tile_loc tile_loc(ix, iy, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); bool skip_add_pb = false; vtr::Point curr_tile_coord(ix, iy); vtr::Point curr_gsb_coord(ix, iy - 1); @@ -56,15 +58,15 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, "programmable block\n", curr_tile_coord.x(), curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); - } else if ((0 < grids.get_width_offset(ix, iy)) || - (0 < grids.get_height_offset(ix, iy))) { + } else if ((0 < grids.get_width_offset(tile_loc)) || + (0 < grids.get_height_offset(tile_loc))) { /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ /* Find the root of this grid, the instance id should be valid. * We just copy it here */ vtr::Point root_tile_coord( - ix - grids.get_width_offset(ix, iy), - iy - grids.get_height_offset(ix, iy)); + ix - grids.get_width_offset(tile_loc), + iy - grids.get_height_offset(tile_loc)); skip_add_pb = true; VTR_LOGV(verbose, "Tile[%lu][%lu] contains a heterogeneous block which is " @@ -146,7 +148,7 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config, /* Depending on the selected style, follow different approaches */ if (tile_config.style() == TileConfig::e_style::TOP_LEFT) { - status_code = build_fabric_tile_style_top_left(fabric_tile, grids, + status_code = build_fabric_tile_style_top_left(fabric_tile, grids, 0, device_rr_gsb, verbose); } else { /* Error out for styles that are not supported yet! */ diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index 64a1472ea..cf7585b9e 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -77,7 +77,7 @@ std::string generate_sb_module_grid_port_name( int pin_id = rr_graph.node_pin_num(rr_node); e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node); t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type( - rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node)); + t_physical_tile_loc(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node))); int pin_width_offset = physical_tile->pin_width_offset[pin_id]; int pin_height_offset = physical_tile->pin_height_offset[pin_id]; BasicPort pin_info = @@ -110,8 +110,8 @@ std::string generate_cb_module_grid_port_name( /* Collect the attributes of the rr_node required to generate the port name */ int pin_id = rr_graph.node_pin_num(rr_node); e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node); - t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type( - rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node)); + t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type(t_physical_tile_loc( + rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node))); int pin_width_offset = physical_tile->pin_width_offset[pin_id]; int pin_height_offset = physical_tile->pin_height_offset[pin_id]; BasicPort pin_info = diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 88858cb0c..1589b7162 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -60,7 +60,8 @@ namespace openfpga { *******************************************************************/ static int build_tile_module_port_and_nets_between_sb_and_pb( ModuleManager& module_manager, const ModuleId& tile_module, - const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const DeviceGrid& grids, const size_t& layer, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const std::vector& pb_instances, @@ -125,7 +126,7 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( rr_gsb.get_opin_node(side_manager.get_side(), inode)); t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; size_t src_grid_pin_height = @@ -287,7 +288,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( *******************************************************************/ static int build_tile_module_port_and_nets_between_cb_and_pb( ModuleManager& module_manager, const ModuleId& tile_module, - const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const DeviceGrid& grids, const size_t& layer, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const t_rr_type& cb_type, @@ -372,7 +374,7 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node); t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; size_t sink_grid_pin_height = @@ -991,14 +993,15 @@ static int build_tile_module_ports_from_cb( ********************************************************************/ static int build_tile_port_and_nets_from_pb( ModuleManager& module_manager, const ModuleId& tile_module, - const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const DeviceGrid& grids, const size_t& layer, + const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, const vtr::Point& pb_coord, const std::vector& pb_instances, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& ipb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = - grids.get_physical_type(pb_coord.x(), pb_coord.y()); + grids.get_physical_type(t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer)); /* Empty type does not require a module */ if (is_empty_type(phy_tile)) { return CMD_EXEC_SUCCESS; @@ -1120,7 +1123,7 @@ static int build_tile_port_and_nets_from_pb( size_t num_fanout_in_tile = module_manager.module_net_sinks(tile_module, curr_net).size(); RRNodeId rr_node = rr_graph.node_lookup().find_node( - pb_coord.x() + iwidth, pb_coord.y() + iheight, OPIN, ipin, + layer, pb_coord.x() + iwidth, pb_coord.y() + iheight, OPIN, ipin, side); size_t num_fanout_required = rr_graph.node_out_edges(rr_node).size(); @@ -1179,7 +1182,8 @@ static int build_tile_port_and_nets_from_pb( *******************************************************************/ static int build_tile_module_ports_and_nets( ModuleManager& module_manager, const ModuleId& tile_module, - const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const DeviceGrid& grids, const size_t& layer, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const std::vector& pb_instances, @@ -1196,7 +1200,7 @@ static int build_tile_module_ports_and_nets( fabric_tile.sb_coordinates(fabric_tile_id)[isb]; const RRGSB& rr_gsb = device_rr_gsb.get_gsb(sb_coord); status_code = build_tile_module_port_and_nets_between_sb_and_pb( - module_manager, tile_module, grids, vpr_device_annotation, device_rr_gsb, + module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, pb_instances, sb_instances, isb, true, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { @@ -1213,7 +1217,7 @@ static int build_tile_module_ports_and_nets( fabric_tile.cb_coordinates(fabric_tile_id, cb_type)[icb]; const RRGSB& rr_gsb = device_rr_gsb.get_gsb(cb_coord); status_code = build_tile_module_port_and_nets_between_cb_and_pb( - module_manager, tile_module, grids, vpr_device_annotation, + module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, cb_type, pb_instances, cb_instances, icb, true, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { @@ -1244,7 +1248,7 @@ static int build_tile_module_ports_and_nets( vtr::Point pb_coord = fabric_tile.pb_coordinates(fabric_tile_id)[ipb]; status_code = build_tile_port_and_nets_from_pb( - module_manager, tile_module, grids, vpr_device_annotation, rr_graph_view, + module_manager, tile_module, grids, layer, vpr_device_annotation, rr_graph_view, pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { @@ -1285,7 +1289,8 @@ static int build_tile_module_ports_and_nets( static int build_tile_module( ModuleManager& module_manager, DecoderLibrary& decoder_lib, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, - const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const DeviceGrid& grids, const size_t& layer, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, const bool& frame_view, @@ -1304,7 +1309,7 @@ static int build_tile_module( for (vtr::Point grid_coord : fabric_tile.pb_coordinates(fabric_tile_id)) { t_physical_tile_type_ptr phy_tile = - grids.get_physical_type(grid_coord.x(), grid_coord.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); VTR_LOGV(verbose, "Try to find pb at [%lu][%lu]\n", grid_coord.x(), grid_coord.y()); /* Empty type does not require a module */ @@ -1433,7 +1438,7 @@ static int build_tile_module( /* Add module nets and ports */ status_code = build_tile_module_ports_and_nets( - module_manager, tile_module, grids, vpr_device_annotation, device_rr_gsb, + module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, fabric_tile, fabric_tile_id, pb_instances, cb_instances, sb_instances, frame_view, verbose); @@ -1512,10 +1517,12 @@ int build_tile_modules(ModuleManager& module_manager, int status_code = CMD_EXEC_SUCCESS; + size_t layer = 0; + /* Build a module for each unique tile */ for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) { status_code = build_tile_module( - module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, + module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, circuit_lib, sram_model, sram_orgz_type, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index e8e5066a1..a81eb86f2 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -71,10 +71,12 @@ int build_top_module( /* Label module usage */ module_manager.set_module_usage(top_module, ModuleManager::MODULE_TOP); + size_t layer = 0; + if (fabric_tile.empty()) { status = build_top_module_fine_grained_child_instances( module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk, - rr_clock_lookup, vpr_device_annotation, grids, tile_annotation, rr_graph, + rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin, fabric_key, group_config_block); @@ -82,7 +84,7 @@ int build_top_module( /* TODO: Build the tile instances under the top module */ status = build_top_module_tile_child_instances( module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk, - rr_clock_lookup, vpr_device_annotation, grids, tile_annotation, rr_graph, + rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol, sram_model, fabric_key, group_config_block, frame_view, verbose); } diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 78e2565d0..4f44f6a41 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -95,7 +95,7 @@ static size_t add_top_module_grid_instance( *******************************************************************/ static vtr::Matrix add_top_module_grid_instances( ModuleManager& module_manager, const ModuleId& top_module, - const DeviceGrid& grids) { + const DeviceGrid& grids, const size_t& layer) { vtr::ScopedStartFinishTimer timer("Add grid instances to top module"); /* Reserve an array for the instance ids */ @@ -109,23 +109,24 @@ static vtr::Matrix add_top_module_grid_instances( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(io_coordinate.x(), io_coordinate.y()); + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { continue; } /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) || - (0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { /* Find the root of this grid, the instance id should be valid. * We just copy it here */ vtr::Point root_grid_coord( io_coordinate.x() - - grids.get_width_offset(io_coordinate.x(), io_coordinate.y()), + grids.get_width_offset(phy_tile_loc), io_coordinate.y() - - grids.get_height_offset(io_coordinate.x(), io_coordinate.y())); + grids.get_height_offset(phy_tile_loc)); VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]); grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = @@ -148,20 +149,21 @@ static vtr::Matrix add_top_module_grid_instances( */ for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(ix, iy); + t_physical_tile_loc phy_tile_loc(ix, iy, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { continue; } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(ix, iy)) || - (0 < grids.get_height_offset(ix, iy))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { /* Find the root of this grid, the instance id should be valid. * We just copy it here */ vtr::Point root_grid_coord( - ix - grids.get_width_offset(ix, iy), - iy - grids.get_height_offset(ix, iy)); + ix - grids.get_width_offset(phy_tile_loc), + iy - grids.get_height_offset(phy_tile_loc)); VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]); grid_instance_ids[ix][iy] = @@ -319,22 +321,24 @@ static vtr::Matrix add_top_module_connection_block_instances( *******************************************************************/ static void add_top_module_io_children( ModuleManager& module_manager, const ModuleId& top_module, - const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids) { + const DeviceGrid& grids, const size_t& layer, + const vtr::Matrix& grid_instance_ids) { /* Create the coordinate range for the perimeter I/Os of FPGA fabric */ std::map>> io_coordinates = generate_perimeter_grid_coordinates(grids); for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coord : io_coordinates[io_side]) { + t_physical_tile_loc phy_tile_loc(io_coord.x(), io_coord.y(), layer); t_physical_tile_type_ptr grid_type = - grids.get_physical_type(io_coord.x(), io_coord.y()); + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(grid_type)) { continue; } /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(io_coord.x(), io_coord.y())) || - (0 < grids.get_height_offset(io_coord.x(), io_coord.y()))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } /* Find the module name for this type of grid */ @@ -395,15 +399,16 @@ static void add_top_module_io_children( /* Now walk through the coordinates */ for (vtr::Point coord : coords) { + t_physical_tile_loc phy_tile_loc(coord.x(), coord.y(), layer); t_physical_tile_type_ptr grid_type = - grids.get_physical_type(coord.x(), coord.y()); + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(grid_type)) { continue; } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(coord.x(), coord.y())) || - (0 < grids.get_height_offset(coord.x(), coord.y()))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } /* Find the module name for this type of grid */ @@ -431,6 +436,7 @@ int build_top_module_fine_grained_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, const ArchDirect& arch_direct, const ConfigProtocol& config_protocol, @@ -443,7 +449,7 @@ int build_top_module_fine_grained_child_instances( /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */ /* Add all the grids across the fabric */ vtr::Matrix grid_instance_ids = - add_top_module_grid_instances(module_manager, top_module, grids); + add_top_module_grid_instances(module_manager, top_module, grids, layer); /* Add all the SBs across the fabric */ vtr::Matrix sb_instance_ids = add_top_module_switch_block_instances( module_manager, top_module, device_rr_gsb, compact_routing_hierarchy); @@ -457,7 +463,7 @@ int build_top_module_fine_grained_child_instances( /* Update I/O children list */ add_top_module_io_children(module_manager, top_module, grids, - grid_instance_ids); + layer, grid_instance_ids); /* Add nets when we need a complete fabric modeling, * which is required by downstream functions @@ -468,19 +474,19 @@ int build_top_module_fine_grained_child_instances( /* Add module nets to connect the sub modules */ add_top_module_nets_connect_grids_and_gsbs( - module_manager, top_module, vpr_device_annotation, grids, + module_manager, top_module, vpr_device_annotation, grids, layer, grid_instance_ids, rr_graph, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, duplicate_grid_pin); /* Add inter-CLB direct connections */ add_top_module_nets_tile_direct_connections( module_manager, top_module, circuit_lib, vpr_device_annotation, grids, - grid_instance_ids, tile_direct, arch_direct); + layer, grid_instance_ids, tile_direct, arch_direct); } /* Add global ports from grid ports that are defined as global in tile * annotation */ status = add_top_module_global_ports_from_grid_modules( - module_manager, top_module, tile_annotation, vpr_device_annotation, grids, + module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids, clk_ntwk, rr_clock_lookup); if (CMD_EXEC_FATAL_ERROR == status) { @@ -500,7 +506,7 @@ int build_top_module_fine_grained_child_instances( if (true == fabric_key.empty()) { organize_top_module_memory_modules( module_manager, top_module, circuit_lib, config_protocol, sram_model, - grids, grid_instance_ids, device_rr_gsb, sb_instance_ids, cb_instance_ids, + grids, layer, grid_instance_ids, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy); } else { VTR_ASSERT_SAFE(false == fabric_key.empty()); diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index 41628ac79..648583830 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -38,6 +38,7 @@ int build_top_module_fine_grained_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, const ArchDirect& arch_direct, const ConfigProtocol& config_protocol, diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 664be1ceb..06c73bd6c 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1272,6 +1272,7 @@ static int build_top_module_global_net_for_given_tile_module( const TileGlobalPortId& tile_global_port, const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& grid_coordinate, const e_side& border_side, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile) { /* Get the tile module and instance */ @@ -1298,7 +1299,7 @@ static int build_top_module_global_net_for_given_tile_module( unique_fabric_tile_id)[pb_idx_in_curr_fabric_tile]; t_physical_tile_type_ptr physical_tile = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); /* Find the module name for this type of grid */ std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string grid_instance_name = @@ -1419,6 +1420,7 @@ static int build_top_module_global_net_from_tile_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile) { int status = CMD_EXEC_SUCCESS; @@ -1475,15 +1477,16 @@ static int build_top_module_global_net_from_tile_modules( /* Spot the port from child modules from core grids */ for (size_t ix = start_coord.x(); ix < end_coord.x(); ++ix) { for (size_t iy = start_coord.y(); iy < end_coord.y(); ++iy) { + t_physical_tile_loc phy_tile_loc(ix, iy, layer); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(ix, iy); + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY tiles */ if (true == is_empty_type(phy_tile_type)) { continue; } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(ix, iy)) || - (0 < grids.get_height_offset(ix, iy))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } @@ -1495,7 +1498,7 @@ static int build_top_module_global_net_from_tile_modules( /* Create nets and finish connection build-up */ status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, tile_port, vpr_device_annotation, grids, + tile_global_port, tile_port, vpr_device_annotation, grids, layer, vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, fabric_tile); if (CMD_EXEC_FATAL_ERROR == status) { @@ -1507,8 +1510,9 @@ static int build_top_module_global_net_from_tile_modules( /* Walk through all the grids on the perimeter, which are I/O grids */ for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(io_coordinate.x(), io_coordinate.y()); + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { continue; @@ -1516,9 +1520,9 @@ static int build_top_module_global_net_from_tile_modules( /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ if ((0 < - grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) || + grids.get_width_offset(phy_tile_loc)) || (0 < - grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) { + grids.get_height_offset(phy_tile_loc))) { continue; } @@ -1543,7 +1547,7 @@ static int build_top_module_global_net_from_tile_modules( /* Create nets and finish connection build-up */ status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, tile_port, vpr_device_annotation, grids, + tile_global_port, tile_port, vpr_device_annotation, grids, layer, io_coordinate, io_side, tile_instance_ids, fabric_tile); if (CMD_EXEC_FATAL_ERROR == status) { return status; @@ -1563,6 +1567,7 @@ static int add_top_module_global_ports_from_tile_modules( ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) { @@ -1621,7 +1626,7 @@ static int add_top_module_global_ports_from_tile_modules( } else { status = build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, vpr_device_annotation, grids, tile_instance_ids, + tile_global_port, vpr_device_annotation, grids, layer, tile_instance_ids, fabric_tile); } if (status == CMD_EXEC_FATAL_ERROR) { @@ -1647,6 +1652,7 @@ static void add_module_nets_connect_tile_direct_connection( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const TileDirect& tile_direct, const TileDirectId& tile_direct_id, const ArchDirect& arch_direct) { @@ -1739,8 +1745,9 @@ static void add_module_nets_connect_tile_direct_connection( e_side src_pin_grid_side = tile_direct.from_tile_side(tile_direct_id); size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id); + t_physical_tile_loc src_tile_loc(src_clb_coord.x(), src_clb_coord.y(), layer); t_physical_tile_type_ptr src_grid_type_descriptor = - grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y()); + grids.get_physical_type(src_tile_loc); size_t src_pin_width = src_grid_type_descriptor->pin_width_offset[src_tile_pin]; size_t src_pin_height = @@ -1775,8 +1782,9 @@ static void add_module_nets_connect_tile_direct_connection( e_side sink_pin_grid_side = tile_direct.to_tile_side(tile_direct_id); size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id); + t_physical_tile_loc des_tile_loc(des_clb_coord.x(), des_clb_coord.y(), layer); t_physical_tile_type_ptr sink_grid_type_descriptor = - grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y()); + grids.get_physical_type(des_tile_loc); size_t sink_pin_width = sink_grid_type_descriptor->pin_width_offset[src_tile_pin]; size_t sink_pin_height = @@ -1838,6 +1846,7 @@ static void add_top_module_nets_connect_tile_direct_connections( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const TileDirect& tile_direct, const ArchDirect& arch_direct) { vtr::ScopedStartFinishTimer timer( @@ -1846,7 +1855,7 @@ static void add_top_module_nets_connect_tile_direct_connections( for (const TileDirectId& tile_direct_id : tile_direct.directs()) { add_module_nets_connect_tile_direct_connection( module_manager, top_module, circuit_lib, vpr_device_annotation, grids, - tile_instance_ids, fabric_tile, tile_direct, tile_direct_id, arch_direct); + layer, tile_instance_ids, fabric_tile, tile_direct, tile_direct_id, arch_direct); } } @@ -1860,6 +1869,7 @@ int build_top_module_tile_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, const ArchDirect& arch_direct, const FabricTile& fabric_tile, @@ -1892,7 +1902,7 @@ int build_top_module_tile_child_instances( /* TODO: Inter-tile direct connections */ add_top_module_nets_connect_tile_direct_connections( module_manager, top_module, circuit_lib, vpr_device_annotation, grids, - tile_instance_ids, fabric_tile, tile_direct, arch_direct); + layer, tile_instance_ids, fabric_tile, tile_direct, arch_direct); } /* Add global ports from tile modules: how to connect to clock architecture @@ -1900,7 +1910,7 @@ int build_top_module_tile_child_instances( */ status = add_top_module_global_ports_from_tile_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, - rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, + layer, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, rr_clock_lookup); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index 5adc39c75..e35ad3623 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -38,6 +38,7 @@ int build_top_module_tile_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, const ArchDirect& arch_direct, const FabricTile& fabric_tile, diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index de4402c51..a0afbf79c 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -64,6 +64,7 @@ namespace openfpga { static void add_top_module_nets_connect_grids_and_sb( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb, const vtr::Matrix& sb_instance_ids, @@ -127,7 +128,7 @@ static void add_top_module_nets_connect_grids_and_sb( rr_gsb.get_opin_node(side_manager.get_side(), inode)); t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; size_t src_grid_pin_height = @@ -227,6 +228,7 @@ static void add_top_module_nets_connect_grids_and_sb( static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb, const vtr::Matrix& sb_instance_ids, @@ -300,8 +302,9 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( size_t src_grid_pin_index = rr_graph.node_pin_num( rr_gsb.get_opin_node(side_manager.get_side(), inode)); + t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(phy_tile_loc); size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; size_t src_grid_pin_height = @@ -437,6 +440,7 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( static void add_top_module_nets_connect_grids_and_cb( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb, const t_rr_type& cb_type, const vtr::Matrix& cb_instance_ids, @@ -520,7 +524,7 @@ static void add_top_module_nets_connect_grids_and_cb( size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node); t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; size_t sink_grid_pin_height = @@ -802,6 +806,7 @@ static void add_top_module_nets_connect_sb_and_cb( void add_top_module_nets_connect_grids_and_gsbs( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, @@ -819,24 +824,24 @@ void add_top_module_nets_connect_grids_and_gsbs( if (false == duplicate_grid_pin) { add_top_module_nets_connect_grids_and_sb( module_manager, top_module, vpr_device_annotation, grids, - grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, + layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } else { VTR_ASSERT_SAFE(true == duplicate_grid_pin); add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( module_manager, top_module, vpr_device_annotation, grids, - grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, + layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } add_top_module_nets_connect_grids_and_cb( module_manager, top_module, vpr_device_annotation, grids, - grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX, + layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), compact_routing_hierarchy); add_top_module_nets_connect_grids_and_cb( module_manager, top_module, vpr_device_annotation, grids, - grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY, + layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), compact_routing_hierarchy); add_top_module_nets_connect_sb_and_cb( @@ -856,10 +861,11 @@ static int build_top_module_global_net_for_given_grid_module( const TileGlobalPortId& tile_global_port, const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& grid_coordinate, const e_side& border_side, const vtr::Matrix& grid_instance_ids) { t_physical_tile_type_ptr physical_tile = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); /* Find the module name for this type of grid */ std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string grid_module_name = generate_grid_block_module_name( @@ -982,6 +988,7 @@ static int build_top_module_global_net_from_grid_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids) { int status = CMD_EXEC_SUCCESS; @@ -1038,15 +1045,16 @@ static int build_top_module_global_net_from_grid_modules( /* Spot the port from child modules from core grids */ for (size_t ix = start_coord.x(); ix < end_coord.x(); ++ix) { for (size_t iy = start_coord.y(); iy < end_coord.y(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(ix, iy); + grids.get_physical_type(tile_loc); /* Bypass EMPTY tiles */ if (true == is_empty_type(phy_tile_type)) { continue; } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(ix, iy)) || - (0 < grids.get_height_offset(ix, iy))) { + if ((0 < grids.get_width_offset(tile_loc)) || + (0 < grids.get_height_offset(tile_loc))) { continue; } @@ -1059,7 +1067,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, - vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids); + layer, vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1069,8 +1077,9 @@ static int build_top_module_global_net_from_grid_modules( /* Walk through all the grids on the perimeter, which are I/O grids */ for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + t_physical_tile_loc tile_loc(io_coordinate.x(), io_coordinate.y(), layer); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(io_coordinate.x(), io_coordinate.y()); + grids.get_physical_type(tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { continue; @@ -1078,9 +1087,9 @@ static int build_top_module_global_net_from_grid_modules( /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ if ((0 < - grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) || + grids.get_width_offset(tile_loc)) || (0 < - grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) { + grids.get_height_offset(tile_loc))) { continue; } @@ -1106,7 +1115,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, - io_coordinate, io_side, grid_instance_ids); + layer, io_coordinate, io_side, grid_instance_ids); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1203,6 +1212,7 @@ int add_top_module_global_ports_from_grid_modules( ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, @@ -1262,7 +1272,7 @@ int add_top_module_global_ports_from_grid_modules( } else { status = build_top_module_global_net_from_grid_modules( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, vpr_device_annotation, grids, grid_instance_ids); + tile_global_port, vpr_device_annotation, grids, layer, grid_instance_ids); } if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index a155d6a7d..80659e2bd 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -28,6 +28,7 @@ namespace openfpga { void add_top_module_nets_connect_grids_and_gsbs( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, @@ -37,6 +38,7 @@ int add_top_module_global_ports_from_grid_modules( ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp index 6af69cdb2..20c43e419 100644 --- a/openfpga/src/fabric/build_top_module_directs.cpp +++ b/openfpga/src/fabric/build_top_module_directs.cpp @@ -39,6 +39,7 @@ static void add_module_nets_tile_direct_connection( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, const TileDirectId& tile_direct_id, const ArchDirect& arch_direct) { vtr::Point device_size(grids.width(), grids.height()); @@ -46,8 +47,9 @@ static void add_module_nets_tile_direct_connection( /* Find the module name of source clb */ vtr::Point src_clb_coord = tile_direct.from_tile_coordinate(tile_direct_id); + t_physical_tile_loc src_grid_loc(src_clb_coord.x(), src_clb_coord.y(), layer); t_physical_tile_type_ptr src_grid_type = - grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y()); + grids.get_physical_type(src_grid_loc); e_side src_grid_border_side = find_grid_border_side(device_size, src_clb_coord); std::string src_module_name_prefix(GRID_MODULE_NAME_PREFIX); @@ -63,8 +65,9 @@ static void add_module_nets_tile_direct_connection( /* Find the module name of sink clb */ vtr::Point des_clb_coord = tile_direct.to_tile_coordinate(tile_direct_id); + t_physical_tile_loc sink_grid_loc(des_clb_coord.x(), des_clb_coord.y(), layer); t_physical_tile_type_ptr sink_grid_type = - grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y()); + grids.get_physical_type(sink_grid_loc); e_side sink_grid_border_side = find_grid_border_side(device_size, des_clb_coord); std::string sink_module_name_prefix(GRID_MODULE_NAME_PREFIX); @@ -114,7 +117,7 @@ static void add_module_nets_tile_direct_connection( size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id); t_physical_tile_type_ptr src_grid_type_descriptor = - grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y()); + grids.get_physical_type(src_grid_loc); size_t src_pin_width = src_grid_type_descriptor->pin_width_offset[src_tile_pin]; size_t src_pin_height = @@ -148,7 +151,7 @@ static void add_module_nets_tile_direct_connection( size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id); t_physical_tile_type_ptr sink_grid_type_descriptor = - grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y()); + grids.get_physical_type(sink_grid_loc); size_t sink_pin_width = sink_grid_type_descriptor->pin_width_offset[src_tile_pin]; size_t sink_pin_height = @@ -209,6 +212,7 @@ void add_top_module_nets_tile_direct_connections( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, const ArchDirect& arch_direct) { vtr::ScopedStartFinishTimer timer( @@ -217,7 +221,7 @@ void add_top_module_nets_tile_direct_connections( for (const TileDirectId& tile_direct_id : tile_direct.directs()) { add_module_nets_tile_direct_connection( module_manager, top_module, circuit_lib, vpr_device_annotation, grids, - grid_instance_ids, tile_direct, tile_direct_id, arch_direct); + layer, grid_instance_ids, tile_direct, tile_direct_id, arch_direct); } } diff --git a/openfpga/src/fabric/build_top_module_directs.h b/openfpga/src/fabric/build_top_module_directs.h index 4de48efb7..c9c13d66b 100644 --- a/openfpga/src/fabric/build_top_module_directs.h +++ b/openfpga/src/fabric/build_top_module_directs.h @@ -26,6 +26,7 @@ void add_top_module_nets_tile_direct_connections( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, const ArchDirect& arch_direct); diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 4e0b45c98..447ecd604 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -136,7 +136,9 @@ static void organize_top_module_tile_memory_modules( const vtr::Matrix& grid_instance_ids, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, - const bool& compact_routing_hierarchy, const vtr::Point& tile_coord, + const bool& compact_routing_hierarchy, + const size_t& layer, + const vtr::Point& tile_coord, const e_side& tile_border_side) { vtr::Point gsb_coord_range = device_rr_gsb.get_gsb_range(); @@ -191,8 +193,9 @@ static void organize_top_module_tile_memory_modules( } /* Find the module name for this type of grid */ + t_physical_tile_loc phy_tile_loc(tile_coord.x(), tile_coord.y(), layer); t_physical_tile_type_ptr grid_type = - grids.get_physical_type(tile_coord.x(), tile_coord.y()); + grids.get_physical_type(phy_tile_loc); /* Skip EMPTY Grid */ if (true == is_empty_type(grid_type)) { @@ -200,8 +203,8 @@ static void organize_top_module_tile_memory_modules( } /* Skip width > 1 or height > 1 Grid, which should already been processed when * offset=0 */ - if ((0 < grids.get_width_offset(tile_coord.x(), tile_coord.y())) || - (0 < grids.get_height_offset(tile_coord.x(), tile_coord.y()))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { return; } @@ -437,6 +440,7 @@ void organize_top_module_memory_modules( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, @@ -497,7 +501,7 @@ void organize_top_module_memory_modules( organize_top_module_tile_memory_modules( module_manager, top_module, circuit_lib, config_protocol.type(), sram_model, grids, grid_instance_ids, device_rr_gsb, sb_instance_ids, - cb_instance_ids, compact_routing_hierarchy, io_coord, io_side); + cb_instance_ids, compact_routing_hierarchy, layer, io_coord, io_side); } } @@ -525,7 +529,7 @@ void organize_top_module_memory_modules( organize_top_module_tile_memory_modules( module_manager, top_module, circuit_lib, config_protocol.type(), sram_model, grids, grid_instance_ids, device_rr_gsb, sb_instance_ids, - cb_instance_ids, compact_routing_hierarchy, core_coord, NUM_SIDES); + cb_instance_ids, compact_routing_hierarchy, layer, core_coord, NUM_SIDES); } /* Split memory modules into different regions */ diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index a452588ec..69df431c5 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -32,6 +32,7 @@ void organize_top_module_memory_modules( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const DeviceGrid& grids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index 1fe1bd158..d3c7ac175 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -30,7 +30,7 @@ std::string generate_grid_block_module_name_in_top_module( vtr::Point device_size(grids.width(), grids.height()); e_side border_side = find_grid_border_side(device_size, grid_coord); t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(grid_coord.x(), grid_coord.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), 0)); return generate_grid_block_module_name( prefix, std::string(phy_tile_type->name), is_io_type(phy_tile_type), @@ -52,7 +52,7 @@ std::string generate_grid_module_port_name_in_top_module( const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, const RRNodeId& inode) { t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0)); size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; size_t sink_grid_pin_height = diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index d4a15986f..69e723f05 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -209,7 +209,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, build_grid_bitstream(bitstream_manager, top_block, openfpga_ctx.module_graph(), openfpga_ctx.fabric_tile(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), - vpr_ctx.device().grid, vpr_ctx.atom(), + vpr_ctx.device().grid, 0, vpr_ctx.atom(), openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_clustering_annotation(), openfpga_ctx.vpr_placement_annotation(), diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 80342a20d..7952b108a 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -824,11 +824,12 @@ static void build_physical_block_bitstream( const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, const VprBitstreamAnnotation& bitstream_annotation, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& grid_coord, const e_side& border_side, const bool& verbose) { /* Create a block for the grid in bitstream manager */ t_physical_tile_type_ptr grid_type = - grids.get_physical_type(grid_coord.x(), grid_coord.y()); + grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); /* Early exit if this parent module has no configurable child modules */ @@ -950,7 +951,8 @@ void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, const ModuleManager& module_manager, const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const DeviceGrid& grids, const AtomContext& atom_ctx, + const DeviceGrid& grids, const size_t& layer, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, @@ -960,13 +962,14 @@ void build_grid_bitstream( /* Generate bitstream for the core logic block one by one */ for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + t_physical_tile_loc phy_tile_loc(ix, iy, layer); /* Bypass EMPTY grid */ - if (true == is_empty_type(grids.get_physical_type(ix, iy))) { + if (true == is_empty_type(grids.get_physical_type(phy_tile_loc))) { continue; } /* Skip width > 1 or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(ix, iy)) || - (0 < grids.get_height_offset(ix, iy))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } /* Add a grid module to top_module*/ @@ -993,7 +996,7 @@ void build_grid_bitstream( build_physical_block_bitstream( bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, bitstream_annotation, grids, grid_coord, NUM_SIDES, + place_annotation, bitstream_annotation, grids, layer, grid_coord, NUM_SIDES, verbose); } } @@ -1008,14 +1011,14 @@ void build_grid_bitstream( /* Add instances of I/O grids to top_module */ for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer); /* Bypass EMPTY grid */ - if (true == is_empty_type(grids.get_physical_type(io_coordinate.x(), - io_coordinate.y()))) { + if (true == is_empty_type(grids.get_physical_type(phy_tile_loc))) { continue; } /* Skip height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) || - (0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } /* TODO: If the fabric tile is not empty, find the tile module and create @@ -1040,7 +1043,7 @@ void build_grid_bitstream( build_physical_block_bitstream( bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, bitstream_annotation, grids, io_coordinate, io_side, + place_annotation, bitstream_annotation, grids, layer, io_coordinate, io_side, verbose); } } diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h index e6b882fcd..3a5e38131 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.h @@ -29,7 +29,8 @@ void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, const ModuleManager& module_manager, const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const DeviceGrid& grids, const AtomContext& atom_ctx, + const DeviceGrid& grids, const size_t& layer, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp index 94bda6b5b..59546d3a0 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp @@ -602,16 +602,17 @@ static void print_analysis_sdc_disable_unused_grid( const ModuleManager& module_manager, const e_side& border_side) { /* Validate file stream */ valid_file_stream(fp); - + + t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0); t_physical_tile_type_ptr grid_type = - grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + grids.get_physical_type(phy_tile_loc); /* Bypass conditions for grids : * 1. EMPTY type, which is by nature unused * 2. Offset > 0, which has already been processed when offset = 0 */ if ((true == is_empty_type(grid_type)) || - (0 < grids.get_width_offset(grid_coordinate.x(), grid_coordinate.y())) || - (0 < grids.get_height_offset(grid_coordinate.x(), grid_coordinate.y()))) { + (0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { return; } diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp index e2c46cf12..3d6aaeb79 100644 --- a/openfpga/src/tile_direct/build_tile_direct.cpp +++ b/openfpga/src/tile_direct/build_tile_direct.cpp @@ -168,7 +168,7 @@ static vtr::Point find_grid_coordinate_given_type( continue; } if (wanted_grid_type_name == - std::string(grids.get_physical_type(coord.x(), coord.y())->name)) { + std::string(grids.get_physical_type(t_physical_tile_loc(coord.x(), coord.y(), 0))->name)) { return coord; } } @@ -401,8 +401,9 @@ static void build_inner_column_row_tile_direct( /* Walk through the device fabric and find the grid that fit the source */ for (size_t x = 0; x < device_ctx.grid.width(); ++x) { for (size_t y = 0; y < device_ctx.grid.height(); ++y) { + t_physical_tile_loc from_phy_tile_loc(x, y, 0); t_physical_tile_type_ptr from_phy_tile_type = - device_ctx.grid.get_physical_type(x, y); + device_ctx.grid.get_physical_type(from_phy_tile_loc); /* Bypass empty grid */ if (true == is_empty_type(from_phy_tile_type)) { continue; @@ -420,8 +421,8 @@ static void build_inner_column_row_tile_direct( for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ std::vector from_pins = find_physical_tile_pin_id( - from_phy_tile_type, device_ctx.grid.get_width_offset(x, y), - device_ctx.grid.get_height_offset(x, y), from_tile_port, from_side); + from_phy_tile_type, device_ctx.grid.get_width_offset(from_phy_tile_loc), + device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port, from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { continue; @@ -437,9 +438,9 @@ static void build_inner_column_row_tile_direct( continue; } + t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0); t_physical_tile_type_ptr to_phy_tile_type = - device_ctx.grid.get_physical_type(to_grid_coord.x(), - to_grid_coord.y()); + device_ctx.grid.get_physical_type(to_phy_tile_loc); /* Bypass the grid that does not fit the from_tile name */ if (to_tile_name != std::string(to_phy_tile_type->name)) { continue; @@ -454,9 +455,9 @@ static void build_inner_column_row_tile_direct( std::vector to_pins = find_physical_tile_pin_id(to_phy_tile_type, device_ctx.grid.get_width_offset( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), device_ctx.grid.get_height_offset( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), to_tile_port, to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { @@ -594,13 +595,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ + t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), from_grid_coord.y(), 0); std::vector from_pins = find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - from_grid_coord.x(), from_grid_coord.y()), + from_phy_tile_loc), device_ctx.grid.get_width_offset( - from_grid_coord.x(), from_grid_coord.y()), + from_phy_tile_loc), device_ctx.grid.get_height_offset( - from_grid_coord.x(), from_grid_coord.y()), + from_phy_tile_loc), from_tile_port, from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { @@ -625,13 +627,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ + t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0); std::vector to_pins = find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), device_ctx.grid.get_width_offset( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), device_ctx.grid.get_height_offset( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), to_tile_port, to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { @@ -707,13 +710,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ + t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), from_grid_coord.y(), 0); std::vector from_pins = find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - from_grid_coord.x(), from_grid_coord.y()), + from_phy_tile_loc), device_ctx.grid.get_width_offset( - from_grid_coord.x(), from_grid_coord.y()), + from_phy_tile_loc), device_ctx.grid.get_height_offset( - from_grid_coord.x(), from_grid_coord.y()), + from_phy_tile_loc), from_tile_port, from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { @@ -738,13 +742,14 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ + t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0); std::vector to_pins = find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), device_ctx.grid.get_width_offset( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), device_ctx.grid.get_height_offset( - to_grid_coord.x(), to_grid_coord.y()), + to_phy_tile_loc), to_tile_port, to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 2e599eb1b..8091081fc 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -89,7 +89,7 @@ std::set find_physical_io_tile_located_sides( for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t iy = 1; iy < grids.height() - 1; ++iy) { /* If located in center, we add a NUM_SIDES and finish */ - if (physical_tile == grids.get_physical_type(ix, iy)) { + if (physical_tile == grids.get_physical_type(t_physical_tile_loc(ix, iy, 0))) { io_sides.insert(NUM_SIDES); center_io = true; break; @@ -109,7 +109,7 @@ std::set find_physical_io_tile_located_sides( for (const vtr::Point& io_coordinate : io_coordinates[fpga_side]) { /* If located in center, we add a NUM_SIDES and finish */ if (physical_tile == - grids.get_physical_type(io_coordinate.x(), io_coordinate.y())) { + grids.get_physical_type(t_physical_tile_loc(io_coordinate.x(), io_coordinate.y(), 0))) { io_sides.insert(fpga_side); break; } diff --git a/openfpga/src/vpr_wrapper/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp index e9b5d563a..940fc0644 100644 --- a/openfpga/src/vpr_wrapper/vpr_main.cpp +++ b/openfpga/src/vpr_wrapper/vpr_main.cpp @@ -118,20 +118,15 @@ static int vpr_standalone(int argc, char** argv) { /* Read options, architecture, and circuit netlist */ vpr_init(argc, const_cast(argv), &Options, &vpr_setup, &Arch); - const Netlist<>& net_list = - vpr_setup.RouterOpts.flat_routing - ? (const Netlist<>&)g_vpr_ctx.atom().nlist - : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - if (Options.show_version) { - vpr_free_all(net_list, Arch, vpr_setup); + vpr_free_all(Arch, vpr_setup); return SUCCESS_EXIT_CODE; } bool flow_succeeded = vpr_flow(vpr_setup, Arch); if (!flow_succeeded) { VTR_LOG("VPR failed to implement circuit\n"); - vpr_free_all(net_list, Arch, vpr_setup); + vpr_free_all(Arch, vpr_setup); return UNIMPLEMENTABLE_EXIT_CODE; } @@ -139,43 +134,30 @@ static int vpr_standalone(int argc, char** argv) { print_timing_stats("Flow", timing_ctx.stats); /* free data structures */ - vpr_free_all(net_list, Arch, vpr_setup); + vpr_free_all(Arch, vpr_setup); VTR_LOG("VPR succeeded\n"); } catch (const tatum::Error& tatum_error) { VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str()); - const Netlist<>& net_list = - vpr_setup.RouterOpts.flat_routing - ? (const Netlist<>&)g_vpr_ctx.atom().nlist - : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - vpr_free_all(net_list, Arch, vpr_setup); + vpr_free_all(Arch, vpr_setup); return ERROR_EXIT_CODE; } catch (const VprError& vpr_error) { vpr_print_error(vpr_error); - const Netlist<>& net_list = - vpr_setup.RouterOpts.flat_routing - ? (const Netlist<>&)g_vpr_ctx.atom().nlist - : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - if (vpr_error.type() == VPR_ERROR_INTERRUPTED) { - vpr_free_all(net_list, Arch, vpr_setup); + vpr_free_all(Arch, vpr_setup); return INTERRUPTED_EXIT_CODE; } else { - vpr_free_all(net_list, Arch, vpr_setup); + vpr_free_all(Arch, vpr_setup); return ERROR_EXIT_CODE; } } catch (const vtr::VtrError& vtr_error) { VTR_LOG_ERROR("%s:%d %s\n", vtr_error.filename_c_str(), vtr_error.line(), vtr_error.what()); - const Netlist<>& net_list = - vpr_setup.RouterOpts.flat_routing - ? (const Netlist<>&)g_vpr_ctx.atom().nlist - : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - vpr_free_all(net_list, Arch, vpr_setup); + vpr_free_all(Arch, vpr_setup); return ERROR_EXIT_CODE; } From 94d80a9b7c226b45ba20970724fac8d042e62c1a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Aug 2023 16:28:56 -0700 Subject: [PATCH 3/6] [core] code format --- openfpga/src/annotation/annotate_rr_graph.cpp | 25 +++-- .../annotate_simulation_setting.cpp | 2 +- .../src/annotation/append_clock_rr_graph.cpp | 67 +++++++------- .../annotation/openfpga_annotate_routing.cpp | 12 ++- .../annotation/vpr_placement_annotation.cpp | 5 +- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 33 ++++--- .../fabric/build_fabric_io_location_map.cpp | 6 +- openfpga/src/fabric/build_fabric_tile.cpp | 3 +- .../src/fabric/build_routing_module_utils.cpp | 12 ++- openfpga/src/fabric/build_tile_modules.cpp | 47 +++++----- openfpga/src/fabric/build_top_module.cpp | 15 +-- ...top_module_child_fine_grained_instance.cpp | 43 +++++---- ...d_top_module_child_fine_grained_instance.h | 14 +-- .../build_top_module_child_tile_instance.cpp | 60 ++++++------ .../build_top_module_child_tile_instance.h | 13 ++- .../fabric/build_top_module_connection.cpp | 91 +++++++++---------- .../src/fabric/build_top_module_connection.h | 10 +- .../src/fabric/build_top_module_directs.cpp | 14 +-- .../src/fabric/build_top_module_directs.h | 5 +- .../src/fabric/build_top_module_memory.cpp | 12 +-- openfpga/src/fabric/build_top_module_memory.h | 3 +- .../src/fabric/build_top_module_utils.cpp | 8 +- .../fpga_bitstream/build_grid_bitstream.cpp | 23 +++-- .../src/fpga_bitstream/build_grid_bitstream.h | 3 +- .../src/fpga_sdc/analysis_sdc_grid_writer.cpp | 5 +- .../src/tile_direct/build_tile_direct.cpp | 88 +++++++++--------- .../utils/openfpga_physical_tile_utils.cpp | 7 +- 27 files changed, 309 insertions(+), 317 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 65cbbe01f..b58dbfd8d 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -21,8 +21,7 @@ namespace openfpga { /* Build a RRChan Object with the given channel type and coorindators */ static RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx, - const t_rr_type& chan_type, - const size_t& layer, + const t_rr_type& chan_type, const size_t& layer, vtr::Point& chan_coord) { std::vector chan_rr_nodes; @@ -153,8 +152,8 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y() + 1, OPIN, opin_grid_side[0]); /* Include Grid[x+1][y+1] Left side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, - gsb_coord.y() + 1, OPIN, opin_grid_side[1]); + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, + gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[1]); break; case RIGHT: /* RIGHT = 1 */ @@ -182,12 +181,12 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* include Grid[x+1][y+1] Bottom side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, - gsb_coord.y() + 1, OPIN, opin_grid_side[0]); + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, + gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[0]); /* include Grid[x+1][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, - gsb_coord.y(), OPIN, opin_grid_side[1]); + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, + gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ /* For the border, we should take special care */ @@ -213,8 +212,8 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, opin_grid_side[1] = RIGHT; /* include Grid[x+1][y] Left side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes( - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x() + 1, - gsb_coord.y(), OPIN, opin_grid_side[0]); + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, + gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[0]); /* include Grid[x][y] Right side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes( vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, gsb_coord.x(), @@ -371,9 +370,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, continue; } /* Collect IPIN rr_nodes*/ - temp_ipin_rr_nodes = - find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, ix, - iy, IPIN, ipin_rr_node_grid_side, include_clock); + temp_ipin_rr_nodes = find_rr_graph_grid_nodes( + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, layer, ix, iy, IPIN, + ipin_rr_node_grid_side, include_clock); /* Fill the ipin nodes of RRGSB */ for (const RRNodeId& inode : temp_ipin_rr_nodes) { /* Skip those has no configurable outgoing, they should NOT appear in the diff --git a/openfpga/src/annotation/annotate_simulation_setting.cpp b/openfpga/src/annotation/annotate_simulation_setting.cpp index 8f4014427..40056f51c 100644 --- a/openfpga/src/annotation/annotate_simulation_setting.cpp +++ b/openfpga/src/annotation/annotate_simulation_setting.cpp @@ -15,8 +15,8 @@ /* Headers from vpr library */ #include "AnalysisDelayCalculator.h" #include "annotate_simulation_setting.h" -#include "net_delay.h" #include "concrete_timing_info.h" +#include "net_delay.h" /* begin namespace openfpga */ namespace openfpga { diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 0f9e1ecbd..a52a86ed2 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -88,9 +88,9 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, static void add_rr_graph_block_clock_nodes( RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const ClockNetwork& clk_ntwk, - const size_t& layer, - const vtr::Point chan_coord, const t_rr_type& chan_type, - const int& cost_index_offset, const bool& verbose) { + const size_t& layer, const vtr::Point chan_coord, + const t_rr_type& chan_type, const int& cost_index_offset, + const bool& verbose) { size_t orig_chan_width = rr_graph_view.node_lookup() .find_channel_nodes(layer, chan_coord.x(), chan_coord.y(), chan_type) @@ -148,14 +148,11 @@ static void add_rr_graph_block_clock_nodes( * Add clock nodes one by one to the routing resource graph. * Assign node-level attributes properly and register in dedicated lookup *******************************************************************/ -static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, - RRClockSpatialLookup& clk_rr_lookup, - const RRGraphView& rr_graph_view, - const DeviceGrid& grids, - const size_t& layer, - const bool& through_channel, - const ClockNetwork& clk_ntwk, - const bool& verbose) { +static void add_rr_graph_clock_nodes( + RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, + const RRGraphView& rr_graph_view, const DeviceGrid& grids, + const size_t& layer, const bool& through_channel, + const ClockNetwork& clk_ntwk, const bool& verbose) { /* Pre-allocate memory: Must do otherwise data will be messed up! */ clk_rr_lookup.reserve_nodes(grids.width(), grids.height(), clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(), @@ -171,9 +168,9 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } - add_rr_graph_block_clock_nodes(rr_graph_builder, clk_rr_lookup, - rr_graph_view, clk_ntwk, layer, chanx_coord, - CHANX, CHANX_COST_INDEX_START, verbose); + add_rr_graph_block_clock_nodes( + rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, + chanx_coord, CHANX, CHANX_COST_INDEX_START, verbose); VTR_ASSERT(rr_graph_view.valid_node( clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); @@ -194,9 +191,9 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, continue; } add_rr_graph_block_clock_nodes( - rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chany_coord, - CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), - verbose); + rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, + chany_coord, CHANY, + CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose); VTR_ASSERT(rr_graph_view.valid_node( clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); @@ -397,11 +394,11 @@ static std::vector find_clock_track2track_node( static void try_find_and_add_clock_track2ipin_node( std::vector& des_nodes, const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, - const vtr::Point& grid_coord, - const e_side& pin_side, const ClockNetwork& clk_ntwk, - const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) { - t_physical_tile_type_ptr grid_type = - grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + const vtr::Point& grid_coord, const e_side& pin_side, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockTreePinId& clk_pin) { + t_physical_tile_type_ptr grid_type = grids.get_physical_type( + t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) { /* tap pin name could be 'io[5:5].a2f[0]' */ @@ -445,17 +442,17 @@ static void try_find_and_add_clock_track2ipin_node( *******************************************************************/ static std::vector find_clock_track2ipin_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, - const t_rr_type& chan_type, const size_t& layer, const vtr::Point& chan_coord, - const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, - const ClockTreePinId& clk_pin) { + const t_rr_type& chan_type, const size_t& layer, + const vtr::Point& chan_coord, const ClockNetwork& clk_ntwk, + const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) { std::vector des_nodes; if (chan_type == CHANX) { /* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */ vtr::Point bot_grid_coord(chan_coord.x(), chan_coord.y() + 1); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, bot_grid_coord, BOTTOM, clk_ntwk, - clk_tree, clk_pin); + layer, bot_grid_coord, BOTTOM, + clk_ntwk, clk_tree, clk_pin); /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */ vtr::Point top_grid_coord(chan_coord.x(), chan_coord.y()); @@ -467,14 +464,14 @@ static std::vector find_clock_track2ipin_node( /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */ vtr::Point left_grid_coord(chan_coord.x() + 1, chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, left_grid_coord, LEFT, clk_ntwk, - clk_tree, clk_pin); + layer, left_grid_coord, LEFT, + clk_ntwk, clk_tree, clk_pin); /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */ vtr::Point right_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, right_grid_coord, RIGHT, clk_ntwk, - clk_tree, clk_pin); + layer, right_grid_coord, RIGHT, + clk_ntwk, clk_tree, clk_pin); } return des_nodes; @@ -486,9 +483,7 @@ static std::vector find_clock_track2ipin_node( static void add_rr_graph_block_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, - const size_t& layer, - const ClockNetwork& clk_ntwk, + const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk, const vtr::Point& chan_coord, const t_rr_type& chan_type, const bool& verbose) { size_t edge_count = 0; @@ -542,8 +537,8 @@ static void add_rr_graph_block_clock_edges( if (clk_ntwk.is_last_level(itree, ilvl)) { size_t curr_edge_count = edge_count; for (RRNodeId des_node : find_clock_track2ipin_node( - grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk, itree, - ClockTreePinId(ipin))) { + grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk, + itree, ClockTreePinId(ipin))) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge(src_node, des_node, diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index e4aa8e88d..f95b2ea37 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -3,8 +3,9 @@ * from VPR to OpenFPGA *******************************************************************/ #include "openfpga_annotate_routing.h" -#include "old_traceback.h" + #include "annotate_routing.h" +#include "old_traceback.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -133,14 +134,17 @@ void annotate_rr_node_previous_nodes( /* Cache Previous nodes */ RRNodeId prev_node = RRNodeId::INVALID(); - t_trace* tptr = TracebackCompat::traceback_from_route_tree(routing_ctx.route_trees[net_id].value()); + t_trace* tptr = TracebackCompat::traceback_from_route_tree( + routing_ctx.route_trees[net_id].value()); while (tptr != nullptr) { RRNodeId rr_node = RRNodeId(tptr->index); /* Find the right previous node */ prev_node = find_previous_node_from_routing_traces( - device_ctx.rr_graph, TracebackCompat::traceback_from_route_tree(routing_ctx.route_trees[net_id].value()), prev_node, - rr_node); + device_ctx.rr_graph, + TracebackCompat::traceback_from_route_tree( + routing_ctx.route_trees[net_id].value()), + prev_node, rr_node); /* Only update mapped nodes */ if (prev_node) { diff --git a/openfpga/src/annotation/vpr_placement_annotation.cpp b/openfpga/src/annotation/vpr_placement_annotation.cpp index 0f24b05fd..4967732b0 100644 --- a/openfpga/src/annotation/vpr_placement_annotation.cpp +++ b/openfpga/src/annotation/vpr_placement_annotation.cpp @@ -32,8 +32,9 @@ void VprPlacementAnnotation::init_mapped_blocks(const DeviceGrid& grids) { for (size_t x = 0; x < grids.width(); ++x) { for (size_t y = 0; y < grids.height(); ++y) { /* Deposit invalid ids and we will fill later */ - blocks_[x][y].resize(grids.get_physical_type(t_physical_tile_loc(x, y, 0))->capacity, - ClusterBlockId::INVALID()); + blocks_[x][y].resize( + grids.get_physical_type(t_physical_tile_loc(x, y, 0))->capacity, + ClusterBlockId::INVALID()); } } } diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index b57616f78..e17a22183 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -34,14 +34,13 @@ namespace openfpga { static void update_cluster_pin_with_post_routing_results( const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const VprRoutingAnnotation& vpr_routing_annotation, - VprClusteringAnnotation& vpr_clustering_annotation, - const size_t& layer, + VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer, const vtr::Point& grid_coord, const ClusterBlockId& blk_id, const e_side& border_side, const size_t& z, const bool& verbose) { /* Handle each pin */ auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id); - auto physical_tile = - device_ctx.grid.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + auto physical_tile = device_ctx.grid.get_physical_type( + t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (int j = 0; j < logical_block->pb_type->num_pins; j++) { /* Get the ptc num for the pin in rr_graph, we need t consider the z offset @@ -87,7 +86,8 @@ static void update_cluster_pin_with_post_routing_results( /* Find the net mapped to this pin in routing results */ const RRNodeId& rr_node = device_ctx.rr_graph.node_lookup().find_node( - layer, grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side); + layer, grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, + pin_side); if (false == device_ctx.rr_graph.valid_node(rr_node)) { continue; } @@ -197,14 +197,17 @@ void update_pb_pin_with_post_routing_results( /* Update the core logic (center blocks of the FPGA) */ for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) { for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) { - t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type(t_physical_tile_loc(x, y, layer)); + t_physical_tile_type_ptr phy_tile = + device_ctx.grid.get_physical_type(t_physical_tile_loc(x, y, layer)); /* Bypass the EMPTY tiles */ if (true == is_empty_type(phy_tile)) { continue; } /* Get the mapped blocks to this grid */ - for (int isubtile = 0; isubtile < phy_tile->capacity; ++isubtile) { - ClusterBlockId cluster_blk_id = placement_ctx.grid_blocks.block_at_location({(int)x, (int)y, (int)isubtile, (int)layer}); + for (int isubtile = 0; isubtile < phy_tile->capacity; ++isubtile) { + ClusterBlockId cluster_blk_id = + placement_ctx.grid_blocks.block_at_location( + {(int)x, (int)y, (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { continue; @@ -214,8 +217,9 @@ void update_pb_pin_with_post_routing_results( vtr::Point grid_coord(x, y); update_cluster_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, - vpr_clustering_annotation, layer, grid_coord, cluster_blk_id, NUM_SIDES, - placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, verbose); + vpr_clustering_annotation, layer, grid_coord, cluster_blk_id, + NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, + verbose); } } } @@ -227,14 +231,17 @@ void update_pb_pin_with_post_routing_results( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coord : io_coordinates[io_side]) { t_physical_tile_type_ptr phy_tile_type = - device_ctx.grid.get_physical_type(t_physical_tile_loc(io_coord.x(), io_coord.y(), layer)); + device_ctx.grid.get_physical_type( + t_physical_tile_loc(io_coord.x(), io_coord.y(), layer)); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { continue; } /* Get the mapped blocks to this grid */ - for (int isubtile = 0; isubtile < phy_tile_type->capacity; ++isubtile) { - ClusterBlockId cluster_blk_id = placement_ctx.grid_blocks.block_at_location({(int)io_coord.x(), (int)io_coord.y(), (int)isubtile, (int)layer}); + for (int isubtile = 0; isubtile < phy_tile_type->capacity; ++isubtile) { + ClusterBlockId cluster_blk_id = + placement_ctx.grid_blocks.block_at_location( + {(int)io_coord.x(), (int)io_coord.y(), (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { continue; diff --git a/openfpga/src/fabric/build_fabric_io_location_map.cpp b/openfpga/src/fabric/build_fabric_io_location_map.cpp index 75b8d37ed..88097f976 100644 --- a/openfpga/src/fabric/build_fabric_io_location_map.cpp +++ b/openfpga/src/fabric/build_fabric_io_location_map.cpp @@ -32,7 +32,8 @@ namespace openfpga { *(x, y, z) coordinate to the actual indices *******************************************************************/ static IoLocationMap build_fabric_fine_grained_io_location_map( - const ModuleManager& module_manager, const DeviceGrid& grids, const size_t& layer) { + const ModuleManager& module_manager, const DeviceGrid& grids, + const size_t& layer) { vtr::ScopedStartFinishTimer timer( "Create I/O location mapping for top module"); @@ -154,7 +155,8 @@ static IoLocationMap build_fabric_fine_grained_io_location_map( *(x, y, z) coordinate to the actual indices *******************************************************************/ static IoLocationMap build_fabric_tiled_io_location_map( - const ModuleManager& module_manager, const DeviceGrid& grids, const size_t& layer) { + const ModuleManager& module_manager, const DeviceGrid& grids, + const size_t& layer) { vtr::ScopedStartFinishTimer timer( "Create I/O location mapping for top module"); diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index b1cc7c80e..465cf7cc9 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -38,7 +38,8 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(tile_loc); bool skip_add_pb = false; vtr::Point curr_tile_coord(ix, iy); vtr::Point curr_gsb_coord(ix, iy - 1); diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index cf7585b9e..e1f3db9ad 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -76,8 +76,10 @@ std::string generate_sb_module_grid_port_name( /* Collect the attributes of the rr_node required to generate the port name */ int pin_id = rr_graph.node_pin_num(rr_node); e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node); - t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type( - t_physical_tile_loc(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node))); + t_physical_tile_type_ptr physical_tile = + vpr_device_grid.get_physical_type(t_physical_tile_loc( + rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), + rr_graph.node_layer(rr_node))); int pin_width_offset = physical_tile->pin_width_offset[pin_id]; int pin_height_offset = physical_tile->pin_height_offset[pin_id]; BasicPort pin_info = @@ -110,8 +112,10 @@ std::string generate_cb_module_grid_port_name( /* Collect the attributes of the rr_node required to generate the port name */ int pin_id = rr_graph.node_pin_num(rr_node); e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node); - t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type(t_physical_tile_loc( - rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node))); + t_physical_tile_type_ptr physical_tile = + vpr_device_grid.get_physical_type(t_physical_tile_loc( + rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), + rr_graph.node_layer(rr_node))); int pin_width_offset = physical_tile->pin_width_offset[pin_id]; int pin_height_offset = physical_tile->pin_height_offset[pin_id]; BasicPort pin_info = diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 1589b7162..621621fc1 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -125,8 +125,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( size_t src_grid_pin_index = rr_graph.node_pin_num( rr_gsb.get_opin_node(side_manager.get_side(), inode)); - t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; size_t src_grid_pin_height = @@ -373,8 +373,8 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node); - t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; size_t sink_grid_pin_height = @@ -994,14 +994,13 @@ static int build_tile_module_ports_from_cb( static int build_tile_port_and_nets_from_pb( ModuleManager& module_manager, const ModuleId& tile_module, const DeviceGrid& grids, const size_t& layer, - const VprDeviceAnnotation& vpr_device_annotation, - const RRGraphView& rr_graph, const vtr::Point& pb_coord, - const std::vector& pb_instances, const FabricTile& fabric_tile, - const FabricTileId& curr_fabric_tile_id, const size_t& ipb, - const bool& frame_view, const bool& verbose) { + const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, + const vtr::Point& pb_coord, const std::vector& pb_instances, + const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, + const size_t& ipb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; - t_physical_tile_type_ptr phy_tile = - grids.get_physical_type(t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer)); + t_physical_tile_type_ptr phy_tile = grids.get_physical_type( + t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer)); /* Empty type does not require a module */ if (is_empty_type(phy_tile)) { return CMD_EXEC_SUCCESS; @@ -1123,8 +1122,8 @@ static int build_tile_port_and_nets_from_pb( size_t num_fanout_in_tile = module_manager.module_net_sinks(tile_module, curr_net).size(); RRNodeId rr_node = rr_graph.node_lookup().find_node( - layer, pb_coord.x() + iwidth, pb_coord.y() + iheight, OPIN, ipin, - side); + layer, pb_coord.x() + iwidth, pb_coord.y() + iheight, OPIN, + ipin, side); size_t num_fanout_required = rr_graph.node_out_edges(rr_node).size(); if (num_fanout_in_tile == num_fanout_required) { @@ -1200,9 +1199,9 @@ static int build_tile_module_ports_and_nets( fabric_tile.sb_coordinates(fabric_tile_id)[isb]; const RRGSB& rr_gsb = device_rr_gsb.get_gsb(sb_coord); status_code = build_tile_module_port_and_nets_between_sb_and_pb( - module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, - rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, pb_instances, - sb_instances, isb, true, frame_view, verbose); + module_manager, tile_module, grids, layer, vpr_device_annotation, + device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, + pb_instances, sb_instances, isb, true, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1248,9 +1247,9 @@ static int build_tile_module_ports_and_nets( vtr::Point pb_coord = fabric_tile.pb_coordinates(fabric_tile_id)[ipb]; status_code = build_tile_port_and_nets_from_pb( - module_manager, tile_module, grids, layer, vpr_device_annotation, rr_graph_view, - pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb, frame_view, - verbose); + module_manager, tile_module, grids, layer, vpr_device_annotation, + rr_graph_view, pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb, + frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1308,8 +1307,8 @@ static int build_tile_module( pb_instances; /* Keep tracking the instance id of each pb */ for (vtr::Point grid_coord : fabric_tile.pb_coordinates(fabric_tile_id)) { - t_physical_tile_type_ptr phy_tile = - grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + t_physical_tile_type_ptr phy_tile = grids.get_physical_type( + t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); VTR_LOGV(verbose, "Try to find pb at [%lu][%lu]\n", grid_coord.x(), grid_coord.y()); /* Empty type does not require a module */ @@ -1438,9 +1437,9 @@ static int build_tile_module( /* Add module nets and ports */ status_code = build_tile_module_ports_and_nets( - module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, - rr_graph_view, fabric_tile, fabric_tile_id, pb_instances, cb_instances, - sb_instances, frame_view, verbose); + module_manager, tile_module, grids, layer, vpr_device_annotation, + device_rr_gsb, rr_graph_view, fabric_tile, fabric_tile_id, pb_instances, + cb_instances, sb_instances, frame_view, verbose); /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index a81eb86f2..5d668f2f2 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -76,17 +76,18 @@ int build_top_module( if (fabric_tile.empty()) { status = build_top_module_fine_grained_child_instances( module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk, - rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, - device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model, - frame_view, compact_routing_hierarchy, duplicate_grid_pin, fabric_key, - group_config_block); + rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, + rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol, + sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin, + fabric_key, group_config_block); } else { /* TODO: Build the tile instances under the top module */ status = build_top_module_tile_child_instances( module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk, - rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, - device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol, - sram_model, fabric_key, group_config_block, frame_view, verbose); + rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, + rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile, + config_protocol, sram_model, fabric_key, group_config_block, frame_view, + verbose); } if (status != CMD_EXEC_SUCCESS) { diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 4f44f6a41..97152ebb4 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -109,7 +109,8 @@ static vtr::Matrix add_top_module_grid_instances( for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer); + t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), + layer); t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ @@ -123,10 +124,8 @@ static vtr::Matrix add_top_module_grid_instances( * We just copy it here */ vtr::Point root_grid_coord( - io_coordinate.x() - - grids.get_width_offset(phy_tile_loc), - io_coordinate.y() - - grids.get_height_offset(phy_tile_loc)); + io_coordinate.x() - grids.get_width_offset(phy_tile_loc), + io_coordinate.y() - grids.get_height_offset(phy_tile_loc)); VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]); grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = @@ -150,7 +149,8 @@ static vtr::Matrix add_top_module_grid_instances( for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t iy = 1; iy < grids.height() - 1; ++iy) { t_physical_tile_loc phy_tile_loc(ix, iy, layer); - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(phy_tile_loc); + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(phy_tile_type)) { continue; @@ -400,8 +400,7 @@ static void add_top_module_io_children( /* Now walk through the coordinates */ for (vtr::Point coord : coords) { t_physical_tile_loc phy_tile_loc(coord.x(), coord.y(), layer); - t_physical_tile_type_ptr grid_type = - grids.get_physical_type(phy_tile_loc); + t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ if (true == is_empty_type(grid_type)) { continue; @@ -436,13 +435,13 @@ int build_top_module_fine_grained_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, - const ArchDirect& arch_direct, const ConfigProtocol& config_protocol, - const CircuitModelId& sram_model, const bool& frame_view, - const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, - const FabricKey& fabric_key, const bool& group_config_block) { + const size_t& layer, const TileAnnotation& tile_annotation, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const TileDirect& tile_direct, const ArchDirect& arch_direct, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, + const bool& frame_view, const bool& compact_routing_hierarchy, + const bool& duplicate_grid_pin, const FabricKey& fabric_key, + const bool& group_config_block) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -462,8 +461,8 @@ int build_top_module_fine_grained_child_instances( compact_routing_hierarchy); /* Update I/O children list */ - add_top_module_io_children(module_manager, top_module, grids, - layer, grid_instance_ids); + add_top_module_io_children(module_manager, top_module, grids, layer, + grid_instance_ids); /* Add nets when we need a complete fabric modeling, * which is required by downstream functions @@ -486,9 +485,9 @@ int build_top_module_fine_grained_child_instances( /* Add global ports from grid ports that are defined as global in tile * annotation */ status = add_top_module_global_ports_from_grid_modules( - module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, - rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids, clk_ntwk, - rr_clock_lookup); + module_manager, top_module, tile_annotation, vpr_device_annotation, grids, + layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids, + clk_ntwk, rr_clock_lookup); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -506,8 +505,8 @@ int build_top_module_fine_grained_child_instances( if (true == fabric_key.empty()) { organize_top_module_memory_modules( module_manager, top_module, circuit_lib, config_protocol, sram_model, - grids, layer, grid_instance_ids, device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy); + grids, layer, grid_instance_ids, device_rr_gsb, sb_instance_ids, + cb_instance_ids, compact_routing_hierarchy); } else { VTR_ASSERT_SAFE(false == fabric_key.empty()); /* Throw a fatal error when the fabric key has a mismatch in region diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index 648583830..f54e07c24 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -38,13 +38,13 @@ int build_top_module_fine_grained_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, - const ArchDirect& arch_direct, const ConfigProtocol& config_protocol, - const CircuitModelId& sram_model, const bool& frame_view, - const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, - const FabricKey& fabric_key, const bool& group_config_block); + const size_t& layer, const TileAnnotation& tile_annotation, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const TileDirect& tile_direct, const ArchDirect& arch_direct, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, + const bool& frame_view, const bool& compact_routing_hierarchy, + const bool& duplicate_grid_pin, const FabricKey& fabric_key, + const bool& group_config_block); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 06c73bd6c..9b190c646 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1272,9 +1272,9 @@ static int build_top_module_global_net_for_given_tile_module( const TileGlobalPortId& tile_global_port, const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Point& grid_coordinate, const e_side& border_side, - const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile) { + const size_t& layer, const vtr::Point& grid_coordinate, + const e_side& border_side, const vtr::Matrix& tile_instance_ids, + const FabricTile& fabric_tile) { /* Get the tile module and instance */ FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); @@ -1298,8 +1298,8 @@ static int build_top_module_global_net_for_given_tile_module( fabric_tile.pb_coordinates( unique_fabric_tile_id)[pb_idx_in_curr_fabric_tile]; - t_physical_tile_type_ptr physical_tile = - grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + t_physical_tile_type_ptr physical_tile = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); /* Find the module name for this type of grid */ std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string grid_instance_name = @@ -1420,8 +1420,8 @@ static int build_top_module_global_net_from_tile_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile) { + const size_t& layer, const vtr::Matrix& tile_instance_ids, + const FabricTile& fabric_tile) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1510,7 +1510,8 @@ static int build_top_module_global_net_from_tile_modules( /* Walk through all the grids on the perimeter, which are I/O grids */ for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer); + t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), + layer); t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ @@ -1519,10 +1520,8 @@ static int build_top_module_global_net_from_tile_modules( } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < - grids.get_width_offset(phy_tile_loc)) || - (0 < - grids.get_height_offset(phy_tile_loc))) { + if ((0 < grids.get_width_offset(phy_tile_loc)) || + (0 < grids.get_height_offset(phy_tile_loc))) { continue; } @@ -1567,8 +1566,8 @@ static int add_top_module_global_ports_from_tile_modules( ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const size_t& layer, const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) { int status = CMD_EXEC_SUCCESS; @@ -1626,8 +1625,8 @@ static int add_top_module_global_ports_from_tile_modules( } else { status = build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, vpr_device_annotation, grids, layer, tile_instance_ids, - fabric_tile); + tile_global_port, vpr_device_annotation, grids, layer, + tile_instance_ids, fabric_tile); } if (status == CMD_EXEC_FATAL_ERROR) { return status; @@ -1652,10 +1651,9 @@ static void add_module_nets_connect_tile_direct_connection( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, - const TileDirect& tile_direct, const TileDirectId& tile_direct_id, - const ArchDirect& arch_direct) { + const size_t& layer, const vtr::Matrix& tile_instance_ids, + const FabricTile& fabric_tile, const TileDirect& tile_direct, + const TileDirectId& tile_direct_id, const ArchDirect& arch_direct) { vtr::Point device_size(grids.width(), grids.height()); std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); @@ -1846,16 +1844,17 @@ static void add_top_module_nets_connect_tile_direct_connections( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, - const TileDirect& tile_direct, const ArchDirect& arch_direct) { + const size_t& layer, const vtr::Matrix& tile_instance_ids, + const FabricTile& fabric_tile, const TileDirect& tile_direct, + const ArchDirect& arch_direct) { vtr::ScopedStartFinishTimer timer( "Add module nets for inter-tile connections"); for (const TileDirectId& tile_direct_id : tile_direct.directs()) { add_module_nets_connect_tile_direct_connection( module_manager, top_module, circuit_lib, vpr_device_annotation, grids, - layer, tile_instance_ids, fabric_tile, tile_direct, tile_direct_id, arch_direct); + layer, tile_instance_ids, fabric_tile, tile_direct, tile_direct_id, + arch_direct); } } @@ -1869,13 +1868,12 @@ int build_top_module_tile_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, - const ArchDirect& arch_direct, const FabricTile& fabric_tile, - const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, - const FabricKey& fabric_key, const bool& group_config_block, - const bool& frame_view, const bool& verbose) { + const size_t& layer, const TileAnnotation& tile_annotation, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const TileDirect& tile_direct, const ArchDirect& arch_direct, + const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, + const CircuitModelId& sram_model, const FabricKey& fabric_key, + const bool& group_config_block, const bool& frame_view, const bool& verbose) { int status = CMD_EXEC_SUCCESS; vtr::Matrix tile_instance_ids; status = add_top_module_tile_instances(module_manager, top_module, diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index e35ad3623..57d3604e4 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -38,13 +38,12 @@ int build_top_module_tile_child_instances( const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, - const ArchDirect& arch_direct, const FabricTile& fabric_tile, - const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, - const FabricKey& fabric_key, const bool& group_config_block, - const bool& frame_view, const bool& verbose); + const size_t& layer, const TileAnnotation& tile_annotation, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const TileDirect& tile_direct, const ArchDirect& arch_direct, + const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, + const CircuitModelId& sram_model, const FabricKey& fabric_key, + const bool& group_config_block, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index a0afbf79c..c2d029d92 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -64,10 +64,9 @@ namespace openfpga { static void add_top_module_nets_connect_grids_and_sb( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb, - const vtr::Matrix& sb_instance_ids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const RRGSB& rr_gsb, const vtr::Matrix& sb_instance_ids, const bool& compact_routing_hierarchy) { /* Skip those Switch blocks that do not exist */ if (false == rr_gsb.is_sb_exist()) { @@ -127,8 +126,8 @@ static void add_top_module_nets_connect_grids_and_sb( size_t src_grid_pin_index = rr_graph.node_pin_num( rr_gsb.get_opin_node(side_manager.get_side(), inode)); - t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; size_t src_grid_pin_height = @@ -228,10 +227,9 @@ static void add_top_module_nets_connect_grids_and_sb( static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb, - const vtr::Matrix& sb_instance_ids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const RRGSB& rr_gsb, const vtr::Matrix& sb_instance_ids, const bool& compact_routing_hierarchy) { /* Skip those Switch blocks that do not exist */ if (false == rr_gsb.is_sb_exist()) { @@ -302,7 +300,8 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( size_t src_grid_pin_index = rr_graph.node_pin_num( rr_gsb.get_opin_node(side_manager.get_side(), inode)); - t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); + t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(), + layer); t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type(phy_tile_loc); size_t src_grid_pin_width = @@ -440,10 +439,10 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( static void add_top_module_nets_connect_grids_and_cb( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const RRGSB& rr_gsb, - const t_rr_type& cb_type, const vtr::Matrix& cb_instance_ids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const RRGSB& rr_gsb, const t_rr_type& cb_type, + const vtr::Matrix& cb_instance_ids, const bool& compact_routing_hierarchy) { /* We could have two different coordinators, one is the instance, the other is * the module */ @@ -523,8 +522,8 @@ static void add_top_module_nets_connect_grids_and_cb( grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node); - t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; size_t sink_grid_pin_height = @@ -806,9 +805,9 @@ static void add_top_module_nets_connect_sb_and_cb( void add_top_module_nets_connect_grids_and_gsbs( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin) { vtr::ScopedStartFinishTimer timer("Add module nets between grids and GSBs"); @@ -823,25 +822,25 @@ void add_top_module_nets_connect_grids_and_gsbs( /* Connect the grid pins of the GSB to adjacent grids */ if (false == duplicate_grid_pin) { add_top_module_nets_connect_grids_and_sb( - module_manager, top_module, vpr_device_annotation, grids, - layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, + module_manager, top_module, vpr_device_annotation, grids, layer, + grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } else { VTR_ASSERT_SAFE(true == duplicate_grid_pin); add_top_module_nets_connect_grids_and_sb_with_duplicated_pins( - module_manager, top_module, vpr_device_annotation, grids, - layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, + module_manager, top_module, vpr_device_annotation, grids, layer, + grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } add_top_module_nets_connect_grids_and_cb( - module_manager, top_module, vpr_device_annotation, grids, - layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX, + module_manager, top_module, vpr_device_annotation, grids, layer, + grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), compact_routing_hierarchy); add_top_module_nets_connect_grids_and_cb( - module_manager, top_module, vpr_device_annotation, grids, - layer, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY, + module_manager, top_module, vpr_device_annotation, grids, layer, + grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), compact_routing_hierarchy); add_top_module_nets_connect_sb_and_cb( @@ -861,11 +860,10 @@ static int build_top_module_global_net_for_given_grid_module( const TileGlobalPortId& tile_global_port, const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Point& grid_coordinate, const e_side& border_side, - const vtr::Matrix& grid_instance_ids) { - t_physical_tile_type_ptr physical_tile = - grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + const size_t& layer, const vtr::Point& grid_coordinate, + const e_side& border_side, const vtr::Matrix& grid_instance_ids) { + t_physical_tile_type_ptr physical_tile = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); /* Find the module name for this type of grid */ std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string grid_module_name = generate_grid_block_module_name( @@ -988,8 +986,7 @@ static int build_top_module_global_net_from_grid_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids) { + const size_t& layer, const vtr::Matrix& grid_instance_ids) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1066,8 +1063,8 @@ static int build_top_module_global_net_from_grid_modules( /* Create nets and finish connection build-up */ status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, tile_port, vpr_device_annotation, grids, - layer, vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids); + tile_global_port, tile_port, vpr_device_annotation, grids, layer, + vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1077,7 +1074,8 @@ static int build_top_module_global_net_from_grid_modules( /* Walk through all the grids on the perimeter, which are I/O grids */ for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - t_physical_tile_loc tile_loc(io_coordinate.x(), io_coordinate.y(), layer); + t_physical_tile_loc tile_loc(io_coordinate.x(), io_coordinate.y(), + layer); t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); /* Bypass EMPTY grid */ @@ -1086,10 +1084,8 @@ static int build_top_module_global_net_from_grid_modules( } /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < - grids.get_width_offset(tile_loc)) || - (0 < - grids.get_height_offset(tile_loc))) { + if ((0 < grids.get_width_offset(tile_loc)) || + (0 < grids.get_height_offset(tile_loc))) { continue; } @@ -1114,8 +1110,8 @@ static int build_top_module_global_net_from_grid_modules( /* Create nets and finish connection build-up */ status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, tile_port, vpr_device_annotation, grids, - layer, io_coordinate, io_side, grid_instance_ids); + tile_global_port, tile_port, vpr_device_annotation, grids, layer, + io_coordinate, io_side, grid_instance_ids); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1212,8 +1208,8 @@ int add_top_module_global_ports_from_grid_modules( ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const size_t& layer, const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) { @@ -1272,7 +1268,8 @@ int add_top_module_global_ports_from_grid_modules( } else { status = build_top_module_global_net_from_grid_modules( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, vpr_device_annotation, grids, layer, grid_instance_ids); + tile_global_port, vpr_device_annotation, grids, layer, + grid_instance_ids); } if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index 80659e2bd..d4c18e7a7 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -28,9 +28,9 @@ namespace openfpga { void add_top_module_nets_connect_grids_and_gsbs( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin); @@ -38,8 +38,8 @@ int add_top_module_global_ports_from_grid_modules( ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, + const size_t& layer, const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup); diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp index 20c43e419..205c54702 100644 --- a/openfpga/src/fabric/build_top_module_directs.cpp +++ b/openfpga/src/fabric/build_top_module_directs.cpp @@ -39,9 +39,9 @@ static void add_module_nets_tile_direct_connection( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, - const TileDirectId& tile_direct_id, const ArchDirect& arch_direct) { + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const TileDirect& tile_direct, const TileDirectId& tile_direct_id, + const ArchDirect& arch_direct) { vtr::Point device_size(grids.width(), grids.height()); /* Find the module name of source clb */ @@ -65,7 +65,8 @@ static void add_module_nets_tile_direct_connection( /* Find the module name of sink clb */ vtr::Point des_clb_coord = tile_direct.to_tile_coordinate(tile_direct_id); - t_physical_tile_loc sink_grid_loc(des_clb_coord.x(), des_clb_coord.y(), layer); + t_physical_tile_loc sink_grid_loc(des_clb_coord.x(), des_clb_coord.y(), + layer); t_physical_tile_type_ptr sink_grid_type = grids.get_physical_type(sink_grid_loc); e_side sink_grid_border_side = @@ -212,9 +213,8 @@ void add_top_module_nets_tile_direct_connections( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, - const ArchDirect& arch_direct) { + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const TileDirect& tile_direct, const ArchDirect& arch_direct) { vtr::ScopedStartFinishTimer timer( "Add module nets for inter-tile connections"); diff --git a/openfpga/src/fabric/build_top_module_directs.h b/openfpga/src/fabric/build_top_module_directs.h index c9c13d66b..7e85661dc 100644 --- a/openfpga/src/fabric/build_top_module_directs.h +++ b/openfpga/src/fabric/build_top_module_directs.h @@ -26,9 +26,8 @@ void add_top_module_nets_tile_direct_connections( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, - const ArchDirect& arch_direct); + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const TileDirect& tile_direct, const ArchDirect& arch_direct); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 447ecd604..094a5ea05 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -136,10 +136,8 @@ static void organize_top_module_tile_memory_modules( const vtr::Matrix& grid_instance_ids, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, - const bool& compact_routing_hierarchy, - const size_t& layer, - const vtr::Point& tile_coord, - const e_side& tile_border_side) { + const bool& compact_routing_hierarchy, const size_t& layer, + const vtr::Point& tile_coord, const e_side& tile_border_side) { vtr::Point gsb_coord_range = device_rr_gsb.get_gsb_range(); vtr::Point gsb_coord(tile_coord.x(), tile_coord.y() - 1); @@ -194,8 +192,7 @@ static void organize_top_module_tile_memory_modules( /* Find the module name for this type of grid */ t_physical_tile_loc phy_tile_loc(tile_coord.x(), tile_coord.y(), layer); - t_physical_tile_type_ptr grid_type = - grids.get_physical_type(phy_tile_loc); + t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc); /* Skip EMPTY Grid */ if (true == is_empty_type(grid_type)) { @@ -440,8 +437,7 @@ void organize_top_module_memory_modules( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, const bool& compact_routing_hierarchy) { diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index 69df431c5..3f53e3a42 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -32,8 +32,7 @@ void organize_top_module_memory_modules( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const DeviceGrid& grids, - const size_t& layer, - const vtr::Matrix& grid_instance_ids, + const size_t& layer, const vtr::Matrix& grid_instance_ids, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& sb_instance_ids, const std::map>& cb_instance_ids, const bool& compact_routing_hierarchy); diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index d3c7ac175..ebf52eb77 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -29,8 +29,8 @@ std::string generate_grid_block_module_name_in_top_module( /* Determine if the grid locates at the border */ vtr::Point device_size(grids.width(), grids.height()); e_side border_side = find_grid_border_side(device_size, grid_coord); - t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), 0)); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type( + t_physical_tile_loc(grid_coord.x(), grid_coord.y(), 0)); return generate_grid_block_module_name( prefix, std::string(phy_tile_type->name), is_io_type(phy_tile_type), @@ -51,8 +51,8 @@ std::string generate_grid_module_port_name_in_top_module( const size_t& sink_grid_pin_index, const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, const RRNodeId& inode) { - t_physical_tile_type_ptr grid_type_descriptor = - grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0)); + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0)); size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; size_t sink_grid_pin_height = diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 7952b108a..df3f070aa 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -824,12 +824,11 @@ static void build_physical_block_bitstream( const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, const VprBitstreamAnnotation& bitstream_annotation, const DeviceGrid& grids, - const size_t& layer, - const vtr::Point& grid_coord, const e_side& border_side, - const bool& verbose) { + const size_t& layer, const vtr::Point& grid_coord, + const e_side& border_side, const bool& verbose) { /* Create a block for the grid in bitstream manager */ - t_physical_tile_type_ptr grid_type = - grids.get_physical_type(t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + t_physical_tile_type_ptr grid_type = grids.get_physical_type( + t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); /* Early exit if this parent module has no configurable child modules */ @@ -951,8 +950,7 @@ void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, const ModuleManager& module_manager, const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const DeviceGrid& grids, const size_t& layer, - const AtomContext& atom_ctx, + const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, @@ -996,8 +994,8 @@ void build_grid_bitstream( build_physical_block_bitstream( bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, bitstream_annotation, grids, layer, grid_coord, NUM_SIDES, - verbose); + place_annotation, bitstream_annotation, grids, layer, grid_coord, + NUM_SIDES, verbose); } } VTR_LOGV(verbose, "Done\n"); @@ -1011,7 +1009,8 @@ void build_grid_bitstream( /* Add instances of I/O grids to top_module */ for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), layer); + t_physical_tile_loc phy_tile_loc(io_coordinate.x(), io_coordinate.y(), + layer); /* Bypass EMPTY grid */ if (true == is_empty_type(grids.get_physical_type(phy_tile_loc))) { continue; @@ -1043,8 +1042,8 @@ void build_grid_bitstream( build_physical_block_bitstream( bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, bitstream_annotation, grids, layer, io_coordinate, io_side, - verbose); + place_annotation, bitstream_annotation, grids, layer, io_coordinate, + io_side, verbose); } } VTR_LOGV(verbose, "Done\n"); diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h index 3a5e38131..a3f4f2603 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.h @@ -29,8 +29,7 @@ void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, const ModuleManager& module_manager, const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const DeviceGrid& grids, const size_t& layer, - const AtomContext& atom_ctx, + const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp index 59546d3a0..2de04a881 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp @@ -602,10 +602,9 @@ static void print_analysis_sdc_disable_unused_grid( const ModuleManager& module_manager, const e_side& border_side) { /* Validate file stream */ valid_file_stream(fp); - + t_physical_tile_loc phy_tile_loc(grid_coordinate.x(), grid_coordinate.y(), 0); - t_physical_tile_type_ptr grid_type = - grids.get_physical_type(phy_tile_loc); + t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc); /* Bypass conditions for grids : * 1. EMPTY type, which is by nature unused * 2. Offset > 0, which has already been processed when offset = 0 diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp index 3d6aaeb79..73b5fd77a 100644 --- a/openfpga/src/tile_direct/build_tile_direct.cpp +++ b/openfpga/src/tile_direct/build_tile_direct.cpp @@ -168,7 +168,9 @@ static vtr::Point find_grid_coordinate_given_type( continue; } if (wanted_grid_type_name == - std::string(grids.get_physical_type(t_physical_tile_loc(coord.x(), coord.y(), 0))->name)) { + std::string( + grids.get_physical_type(t_physical_tile_loc(coord.x(), coord.y(), 0)) + ->name)) { return coord; } } @@ -421,8 +423,10 @@ static void build_inner_column_row_tile_direct( for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ std::vector from_pins = find_physical_tile_pin_id( - from_phy_tile_type, device_ctx.grid.get_width_offset(from_phy_tile_loc), - device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port, from_side); + from_phy_tile_type, + device_ctx.grid.get_width_offset(from_phy_tile_loc), + device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port, + from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { continue; @@ -438,7 +442,8 @@ static void build_inner_column_row_tile_direct( continue; } - t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0); + t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), + to_grid_coord.y(), 0); t_physical_tile_type_ptr to_phy_tile_type = device_ctx.grid.get_physical_type(to_phy_tile_loc); /* Bypass the grid that does not fit the from_tile name */ @@ -452,13 +457,10 @@ static void build_inner_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - std::vector to_pins = - find_physical_tile_pin_id(to_phy_tile_type, - device_ctx.grid.get_width_offset( - to_phy_tile_loc), - device_ctx.grid.get_height_offset( - to_phy_tile_loc), - to_tile_port, to_side); + std::vector to_pins = find_physical_tile_pin_id( + to_phy_tile_type, device_ctx.grid.get_width_offset(to_phy_tile_loc), + device_ctx.grid.get_height_offset(to_phy_tile_loc), to_tile_port, + to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { continue; @@ -595,15 +597,13 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), from_grid_coord.y(), 0); - std::vector from_pins = - find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - from_phy_tile_loc), - device_ctx.grid.get_width_offset( - from_phy_tile_loc), - device_ctx.grid.get_height_offset( - from_phy_tile_loc), - from_tile_port, from_side); + t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), + from_grid_coord.y(), 0); + std::vector from_pins = find_physical_tile_pin_id( + device_ctx.grid.get_physical_type(from_phy_tile_loc), + device_ctx.grid.get_width_offset(from_phy_tile_loc), + device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port, + from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { continue; @@ -627,15 +627,13 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0); - std::vector to_pins = - find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - to_phy_tile_loc), - device_ctx.grid.get_width_offset( - to_phy_tile_loc), - device_ctx.grid.get_height_offset( - to_phy_tile_loc), - to_tile_port, to_side); + t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), + to_grid_coord.y(), 0); + std::vector to_pins = find_physical_tile_pin_id( + device_ctx.grid.get_physical_type(to_phy_tile_loc), + device_ctx.grid.get_width_offset(to_phy_tile_loc), + device_ctx.grid.get_height_offset(to_phy_tile_loc), to_tile_port, + to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { continue; @@ -710,15 +708,13 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), from_grid_coord.y(), 0); - std::vector from_pins = - find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - from_phy_tile_loc), - device_ctx.grid.get_width_offset( - from_phy_tile_loc), - device_ctx.grid.get_height_offset( - from_phy_tile_loc), - from_tile_port, from_side); + t_physical_tile_loc from_phy_tile_loc(from_grid_coord.x(), + from_grid_coord.y(), 0); + std::vector from_pins = find_physical_tile_pin_id( + device_ctx.grid.get_physical_type(from_phy_tile_loc), + device_ctx.grid.get_width_offset(from_phy_tile_loc), + device_ctx.grid.get_height_offset(from_phy_tile_loc), from_tile_port, + from_side); /* If nothing found, we can continue */ if (0 == from_pins.size()) { continue; @@ -742,15 +738,13 @@ static void build_inter_column_row_tile_direct( */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { /* Try to find the pin in this tile */ - t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), to_grid_coord.y(), 0); - std::vector to_pins = - find_physical_tile_pin_id(device_ctx.grid.get_physical_type( - to_phy_tile_loc), - device_ctx.grid.get_width_offset( - to_phy_tile_loc), - device_ctx.grid.get_height_offset( - to_phy_tile_loc), - to_tile_port, to_side); + t_physical_tile_loc to_phy_tile_loc(to_grid_coord.x(), + to_grid_coord.y(), 0); + std::vector to_pins = find_physical_tile_pin_id( + device_ctx.grid.get_physical_type(to_phy_tile_loc), + device_ctx.grid.get_width_offset(to_phy_tile_loc), + device_ctx.grid.get_height_offset(to_phy_tile_loc), to_tile_port, + to_side); /* If nothing found, we can continue */ if (0 == to_pins.size()) { continue; diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 8091081fc..1f539ffcf 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -89,7 +89,8 @@ std::set find_physical_io_tile_located_sides( for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t iy = 1; iy < grids.height() - 1; ++iy) { /* If located in center, we add a NUM_SIDES and finish */ - if (physical_tile == grids.get_physical_type(t_physical_tile_loc(ix, iy, 0))) { + if (physical_tile == + grids.get_physical_type(t_physical_tile_loc(ix, iy, 0))) { io_sides.insert(NUM_SIDES); center_io = true; break; @@ -108,8 +109,8 @@ std::set find_physical_io_tile_located_sides( for (const e_side& fpga_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[fpga_side]) { /* If located in center, we add a NUM_SIDES and finish */ - if (physical_tile == - grids.get_physical_type(t_physical_tile_loc(io_coordinate.x(), io_coordinate.y(), 0))) { + if (physical_tile == grids.get_physical_type(t_physical_tile_loc( + io_coordinate.x(), io_coordinate.y(), 0))) { io_sides.insert(fpga_side); break; } From ff6fa1e90c83c225196d81ebb65d0eebed03b4e0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Aug 2023 22:41:43 -0700 Subject: [PATCH 4/6] [core] fix memory leak --- openfpga/src/annotation/openfpga_annotate_routing.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index f95b2ea37..450f3413a 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -136,6 +136,7 @@ void annotate_rr_node_previous_nodes( t_trace* tptr = TracebackCompat::traceback_from_route_tree( routing_ctx.route_trees[net_id].value()); + t_trace* head = tptr; while (tptr != nullptr) { RRNodeId rr_node = RRNodeId(tptr->index); @@ -159,6 +160,7 @@ void annotate_rr_node_previous_nodes( /* Move on to the next */ tptr = tptr->next; } + free_traceback(head); } VTR_LOG("Done with %d nodes mapping\n", counter); From 1c8c4fedbbba8b608f4b518e143725466edd1458 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Aug 2023 23:01:52 -0700 Subject: [PATCH 5/6] [core] fix memory leak --- openfpga/src/annotation/openfpga_annotate_routing.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 450f3413a..f5299c904 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -143,8 +143,7 @@ void annotate_rr_node_previous_nodes( /* Find the right previous node */ prev_node = find_previous_node_from_routing_traces( device_ctx.rr_graph, - TracebackCompat::traceback_from_route_tree( - routing_ctx.route_trees[net_id].value()), + head, prev_node, rr_node); /* Only update mapped nodes */ From 788e3c17a931016c47f2ffe55562a67638dd79ed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Aug 2023 23:02:20 -0700 Subject: [PATCH 6/6] [core] format --- openfpga/src/annotation/openfpga_annotate_routing.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index f5299c904..780b1d99d 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -142,9 +142,7 @@ void annotate_rr_node_previous_nodes( /* Find the right previous node */ prev_node = find_previous_node_from_routing_traces( - device_ctx.rr_graph, - head, - prev_node, rr_node); + device_ctx.rr_graph, head, prev_node, rr_node); /* Only update mapped nodes */ if (prev_node) {