merge from master
This commit is contained in:
Tarachand Pagarani
commit
9d750db90b
|
|
@ -1,2 +1,23 @@
|
|||
# Ignore everything
|
||||
*
|
||||
**
|
||||
|
||||
# Allow files and directories
|
||||
!/.github/**
|
||||
!/*.*
|
||||
!/abc/abc
|
||||
!/abc/libabc.a
|
||||
!/ace2/ace
|
||||
!/ace2/libace.a
|
||||
!/openfpga/libopenfpga.a
|
||||
!/openfpga/openfpga
|
||||
!/vpr/libvpr.a
|
||||
!/vpr/vpr
|
||||
!/yosys/share/
|
||||
!/yosys/yosys
|
||||
!/yosys/yosys-abc
|
||||
!/yosys/yosys-config
|
||||
!/yosys/yosys-filterlib
|
||||
!/yosys/yosys-smtbmc
|
||||
!/openfpga_flow
|
||||
!/openfpga.sh
|
||||
!/openfpga_flow/
|
||||
|
|
|
|||
|
|
@ -1,115 +1,118 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "Basic regression tests";
|
||||
|
||||
echo -e "Testing configuration chain of a K4N4 FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
|
||||
run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
|
||||
run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing fixed device layout and routing channel width";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs
|
||||
run-task basic_tests/fixed_device_support --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing fabric Verilog generation only";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs
|
||||
run-task basic_tests/generate_fabric --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog testbench generation only";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
|
||||
run-task basic_tests/generate_testbench --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing separated Verilog fabric netlists and testbench locations";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
|
||||
run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
|
||||
run-task basic_tests/fixed_simulation_settings --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Secured FPGA fabrics";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
|
||||
|
||||
|
||||
echo -e "Testing K4 series FPGA";
|
||||
echo -e "Testing K4N4 with facturable LUTs";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
|
||||
echo -e "Testing K4N4 with hard adders";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
|
||||
echo -e "Testing K4N4 without local routing architecture";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
|
||||
echo -e "Testing K4N4 with block RAM";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
|
||||
echo -e "Testing K4N4 with LUTRAM";
|
||||
run-task basic_tests/k4_series/k4n4_lutram --debug --show_thread_logs
|
||||
echo -e "Testing K4N4 with multiple lengths of routing segments";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
|
||||
echo -e "Testing K4N4 with 32-bit fracturable multiplier";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
|
||||
echo -e "Testing K4N5 with pattern based local routing";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
|
||||
run-task basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing different tile organizations";
|
||||
echo -e "Testing tiles with pins only on top and left sides";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
|
||||
echo -e "Testing tiles with pins only on top and right sides";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
|
||||
echo -e "Testing tiles with pins only on bottom and right sides";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
|
||||
echo -e "Testing tiles with I/O in center grid";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/tileable_io --debug --show_thread_logs
|
||||
run-task basic_tests/tile_organization/tileable_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing global port definition from tiles";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
|
||||
run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for running quicklogic device";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py quicklogic_tests/flow_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/flow_test --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
name: linux_build
|
||||
|
||||
# Run CI on
|
||||
# - each push
|
||||
# - each pull request
|
||||
# - scheduled weekly
|
||||
# Run CI on push, PR, and weekly.
|
||||
|
||||
on:
|
||||
push:
|
||||
pull_request:
|
||||
schedule:
|
||||
- cron: '0 0 * * 0 ' # weekly
|
||||
- cron: "0 0 * * 0 " # weekly
|
||||
|
||||
# Environment variables
|
||||
env:
|
||||
|
|
@ -18,123 +16,87 @@ env:
|
|||
|
||||
# Multiple job to tests
|
||||
jobs:
|
||||
change_detect:
|
||||
name: "Detect code changes"
|
||||
runs-on: ubuntu-18.04
|
||||
outputs:
|
||||
# this is output as string, see https://docs.github.com/en/actions/reference/workflow-syntax-for-github-actions#jobsjob_idoutputs
|
||||
source_modified: ${{ steps.changes.outputs.status_code == '1' }}
|
||||
force_upload: false
|
||||
sha_short: ${{ steps.changes.outputs.sha_short }}
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
with:
|
||||
fetch-depth: 0
|
||||
submodules: true
|
||||
- name: Check for source code changes
|
||||
id: changes
|
||||
run: |
|
||||
git diff origin/master HEAD --name-status -- . ':!openfpga_flow' ':!docs'
|
||||
if git diff origin/master HEAD --name-status --exit-code -- . ':!openfpga_flow' ':!docs'; then
|
||||
echo "::set-output name=status_code::0"
|
||||
else
|
||||
echo "::set-output name=status_code::$?"
|
||||
fi
|
||||
if [[ ${GITHUB_REF} == 'refs/heads/master' ]]; then
|
||||
echo "Current brnach is master forcing source_modified"
|
||||
echo "::set-output name=status_code::1"
|
||||
fi
|
||||
echo "::set-output name=sha_short::$(git rev-parse --short HEAD)"
|
||||
# Test the compilation compatibility
|
||||
linux_build:
|
||||
needs: change_detect
|
||||
if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }}
|
||||
name: ${{ matrix.config.name }}
|
||||
runs-on: ${{ matrix.config.os }}
|
||||
|
||||
runs-on: ubuntu-18.04
|
||||
container: ghcr.io/lnis-uofu/openfpga-build-${{ matrix.config.cc}}
|
||||
# Branch on different OS and settings
|
||||
strategy:
|
||||
fail-fast: false
|
||||
matrix:
|
||||
config:
|
||||
- {
|
||||
name: "Build Compatibility: GCC-5 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-ubuntu-18.04-gcc5-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-5", cxx: "g++-5"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "Build Compatibility: GCC-6 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-ubuntu-18.04-gcc6-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-6", cxx: "g++-6"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "Build Compatibility: GCC-7 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-ubuntu-18.04-gcc7-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-7", cxx: "g++-7"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "Build Compatibility: GCC-8 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-ubuntu-18.04-gcc8-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-8", cxx: "g++-8"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "Build Compatibility: GCC-9 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-ubuntu-18.04-gcc9-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-9", cxx: "g++-9"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "Build Compatibility: Clang-6 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-ubuntu-18.04-clang6-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "clang-6.0", cxx: "clang++-6.0"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "Build Compatibility: Clang-8 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-ubuntu-18.04-clang8-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "clang-8", cxx: "clang++-8"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-8", cxx: "g++-8",
|
||||
reg_script: "basic_reg_test.sh"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-fpga-verilog-tests-ubuntu-18.04-gcc8-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-8", cxx: "g++-8",
|
||||
reg_script: "fpga_verilog_reg_test.sh"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-fpga-bitstream-tests-ubuntu-18.04-gcc8-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-8", cxx: "g++-8",
|
||||
reg_script: "fpga_bitstream_reg_test.sh"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-fpga-sdc-tests-ubuntu-18.04-gcc8-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-8", cxx: "g++-8",
|
||||
reg_script: "fpga_sdc_reg_test.sh"
|
||||
}
|
||||
|
||||
- {
|
||||
name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)",
|
||||
artifact: "OpenFPGA-fpga-spice-tests-ubuntu-18.04-gcc8-build.7z",
|
||||
os: ubuntu-18.04,
|
||||
cc: "gcc-8", cxx: "g++-8",
|
||||
reg_script: "fpga_spice_reg_test.sh"
|
||||
}
|
||||
|
||||
|
||||
- name: "Build Compatibility: GCC-5 (Ubuntu 18.04)"
|
||||
cc: gcc-5
|
||||
cxx: g++-5
|
||||
- name: "Build Compatibility: GCC-6 (Ubuntu 18.04)"
|
||||
cc: gcc-6
|
||||
cxx: g++-6
|
||||
- name: "Build Compatibility: GCC-7 (Ubuntu 18.04)"
|
||||
cc: gcc-7
|
||||
cxx: g++-7
|
||||
- name: "Build Compatibility: GCC-8 (Ubuntu 18.04)"
|
||||
cc: gcc-8
|
||||
cxx: g++-8
|
||||
- name: "Build Compatibility: GCC-9 (Ubuntu 18.04)"
|
||||
cc: gcc-9
|
||||
cxx: g++-9
|
||||
- name: "Build Compatibility: Clang-6 (Ubuntu 18.04)"
|
||||
cc: clang-6.0
|
||||
cxx: clang++-6.0
|
||||
- name: "Build Compatibility: Clang-8 (Ubuntu 18.04)"
|
||||
cc: clang-8
|
||||
cxx: clang++-8
|
||||
# Define the steps to run the build job
|
||||
env:
|
||||
CC: ${{ matrix.config.cc }}
|
||||
CXX: ${{ matrix.config.cxx }}
|
||||
CCACHE_COMPRESS: "true"
|
||||
CCACHE_COMPRESSLEVEL: "6"
|
||||
CCACHE_MAXSIZE: "400M"
|
||||
CCACHE_LOGFILE: ccache_log
|
||||
CCACHE_DIR: /__w/OpenFPGA/.ccache
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
with:
|
||||
submodules: true
|
||||
submodules: true
|
||||
|
||||
- name: Install dependency
|
||||
run: source ./.github/workflows/install_dependency.sh
|
||||
|
||||
- name: Checkout CMake version
|
||||
run: cmake --version
|
||||
|
||||
- name: Checkout iVerilog version
|
||||
- name: Dump tool versions
|
||||
run: |
|
||||
iverilog -V
|
||||
vvp -V
|
||||
cmake --version
|
||||
iverilog -V
|
||||
vvp -V
|
||||
|
||||
- name: Prepare ccache timestamp
|
||||
id: ccache_cache_timestamp
|
||||
|
|
@ -146,58 +108,167 @@ jobs:
|
|||
- name: Create CMake build environment
|
||||
# Some projects don't allow in-source building, so create a separate build directory
|
||||
# We'll use this as our working directory for all subsequent commands
|
||||
run: cmake -E make_directory ${{runner.workspace}}/build
|
||||
|
||||
- name: ccache cache files
|
||||
run: cmake -E make_directory build
|
||||
|
||||
- name: Setup ccache
|
||||
uses: actions/cache@v2
|
||||
with:
|
||||
path: ${{runner.workspace}}/.ccache
|
||||
key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
|
||||
path: |
|
||||
/__w/OpenFPGA/.ccache
|
||||
key: ${{ matrix.config.cc }}-ccache-${{ github.ref}}
|
||||
restore-keys: |
|
||||
${{ matrix.config.name }}-ccache-
|
||||
|
||||
# Set up the paths for ccache and control the size under 400MB
|
||||
- name: Configure ccache
|
||||
shell: cmake -P {0}
|
||||
run: |
|
||||
file(TO_CMAKE_PATH ${{runner.workspace}} ccache_basedir)
|
||||
set(ENV{CCACHE_BASEDIR} "${ccache_basedir}")
|
||||
set(ENV{CCACHE_DIR} "${ccache_basedir}/.ccache")
|
||||
set(ENV{CCACHE_COMPRESS} "true")
|
||||
set(ENV{CCACHE_COMPRESSLEVEL} "6")
|
||||
set(ENV{CCACHE_MAXSIZE} "400M")
|
||||
|
||||
execute_process(COMMAND ccache -p)
|
||||
execute_process(COMMAND ccache -z)
|
||||
${{ matrix.config.cc }}-ccache-
|
||||
|
||||
- name: Configure CMake
|
||||
# Use a bash shell so we can use the same syntax for environment variable
|
||||
# access regardless of the host operating system
|
||||
shell: bash
|
||||
working-directory: ${{runner.workspace}}/build
|
||||
# Note the current convention is to use the -S and -B options here to specify source
|
||||
# and build directories, but this is only available with CMake 3.13 and higher.
|
||||
working-directory: build
|
||||
# Note the current convention is to use the -S and -B options here to specify source
|
||||
# and build directories, but this is only available with CMake 3.13 and higher.
|
||||
# The CMake binaries on the Github Actions machines are (as of this writing) 3.12
|
||||
#
|
||||
run: |
|
||||
export CC=${{ matrix.config.cc }}
|
||||
export CXX=${{ matrix.config.cxx }}
|
||||
cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache
|
||||
ccache -p
|
||||
ccache -z
|
||||
cmake .. -DCMAKE_BUILD_TYPE=$BUILD_TYPE
|
||||
|
||||
- name: Build
|
||||
working-directory: ${{runner.workspace}}/build
|
||||
working-directory: build
|
||||
shell: bash
|
||||
# Execute the build. You can specify a specific target with "--target <NAME>"
|
||||
run: |
|
||||
cmake --build . --config $BUILD_TYPE
|
||||
cmake --build . --config $BUILD_TYPE
|
||||
|
||||
# Check the cache size and see if it is over the limit
|
||||
- name: Check ccache size
|
||||
shell: cmake -P {0}
|
||||
run: ccache -s
|
||||
- name: Upload artifact
|
||||
uses: actions/upload-artifact@v2
|
||||
if: ${{ matrix.config.cc == 'gcc-8'}}
|
||||
with:
|
||||
name: openfpga
|
||||
path: |
|
||||
abc/abc
|
||||
abc/libabc.a
|
||||
ace2/ace
|
||||
ace2/libace.a
|
||||
openfpga/libopenfpga.a
|
||||
openfpga/openfpga
|
||||
vpr/libvpr.a
|
||||
vpr/vpr
|
||||
yosys/share/
|
||||
yosys/yosys
|
||||
yosys/yosys-abc
|
||||
yosys/yosys-config
|
||||
yosys/yosys-filterlib
|
||||
yosys/yosys-smtbmc
|
||||
openfpga_flow
|
||||
openfpga.sh
|
||||
docker_distribution:
|
||||
name: Build docker image for distribution
|
||||
runs-on: ubuntu-latest
|
||||
needs: [linux_build, change_detect]
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
- name: Download a built artifacts
|
||||
uses: actions/download-artifact@v2
|
||||
with:
|
||||
name: openfpga
|
||||
- name: Set up QEMU
|
||||
uses: docker/setup-qemu-action@v1
|
||||
- name: Set up Docker Buildx
|
||||
uses: docker/setup-buildx-action@v1
|
||||
- name: Login to GitHub Container Registry
|
||||
uses: docker/login-action@v1
|
||||
with:
|
||||
registry: ghcr.io
|
||||
username: ${{ github.repository_owner }}
|
||||
password: ${{ secrets.CR_PAT }}
|
||||
- name: Build and push master image
|
||||
uses: docker/build-push-action@v2
|
||||
with:
|
||||
context: .
|
||||
file: ./docker/Dockerfile.master
|
||||
push: ${{ github.ref == 'refs/heads/master' || needs.change_detect.outputs.force_upload }}
|
||||
tags: |
|
||||
ghcr.io/lnis-uofu/openfpga-master:latest
|
||||
ghcr.io/lnis-uofu/openfpga-master:${{ needs.change_detect.outputs.sha_short }}
|
||||
linux_regression_tests:
|
||||
name: linux_regression_tests
|
||||
runs-on: ubuntu-18.04
|
||||
container: ghcr.io/lnis-uofu/openfpga-env
|
||||
needs: linux_build
|
||||
strategy:
|
||||
fail-fast: false
|
||||
matrix:
|
||||
config:
|
||||
- name: basic_reg_test
|
||||
- name: fpga_verilog_reg_test
|
||||
- name: fpga_bitstream_reg_test
|
||||
- name: fpga_sdc_reg_test
|
||||
- name: fpga_spice_reg_test
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
- name: Download a built artifacts
|
||||
uses: actions/download-artifact@v2
|
||||
with:
|
||||
name: openfpga
|
||||
- name: chmod
|
||||
run: |
|
||||
execute_process(COMMAND ccache -s)
|
||||
|
||||
- name: ${{matrix.config.name}}
|
||||
if: contains(matrix.config.name, 'Regression Test')
|
||||
chmod +x abc/abc
|
||||
chmod +x ace2/ace
|
||||
chmod +x openfpga/openfpga
|
||||
chmod +x vpr/vpr
|
||||
chmod +x yosys/yosys
|
||||
chmod +x yosys/yosys-abc
|
||||
chmod +x yosys/yosys-config
|
||||
chmod +x yosys/yosys-filterlib
|
||||
chmod +x yosys/yosys-smtbmc
|
||||
- name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
|
||||
shell: bash
|
||||
# Execute the test.
|
||||
run: source ./.github/workflows/${{matrix.config.reg_script}}
|
||||
run: source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh
|
||||
- name: Upload artifact
|
||||
uses: actions/upload-artifact@v2
|
||||
if: ${{ failure() }}
|
||||
with:
|
||||
name: failed_${{matrix.config.name}}_regression_log
|
||||
retention-days: 1
|
||||
path: |
|
||||
openfpga_flow/**/*.log
|
||||
docker_regression_tests:
|
||||
needs: change_detect
|
||||
if: ${{ !fromJSON(needs.change_detect.outputs.source_modified) }}
|
||||
name: docker_regression_tests
|
||||
runs-on: ubuntu-18.04
|
||||
container: ghcr.io/lnis-uofu/openfpga-master:latest
|
||||
strategy:
|
||||
fail-fast: false
|
||||
matrix:
|
||||
config:
|
||||
- name: basic_reg_test
|
||||
- name: fpga_verilog_reg_test
|
||||
- name: fpga_bitstream_reg_test
|
||||
- name: fpga_sdc_reg_test
|
||||
- name: fpga_spice_reg_test
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
with:
|
||||
submodules: true
|
||||
- name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
|
||||
shell: bash
|
||||
run: |
|
||||
bash .github/workflows/install_dependencies_run.sh
|
||||
${PYTHON_EXEC} -m pip install -r requirements.txt
|
||||
rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. .
|
||||
source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh
|
||||
- name: Upload artifact
|
||||
uses: actions/upload-artifact@v2
|
||||
if: ${{ failure() }}
|
||||
with:
|
||||
name: failed_${{matrix.config.name}}_regression_log
|
||||
retention-days: 1
|
||||
path: openfpga_flow/**/*.log
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
name: Build docker CI images
|
||||
on:
|
||||
- workflow_dispatch
|
||||
jobs:
|
||||
base_images:
|
||||
name: Push Docker images
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: Checkout
|
||||
uses: actions/checkout@v2
|
||||
- name: Set up QEMU
|
||||
uses: docker/setup-qemu-action@v1
|
||||
- name: Set up Docker Buildx
|
||||
uses: docker/setup-buildx-action@v1
|
||||
- name: Login to GitHub Container Registry
|
||||
uses: docker/login-action@v1
|
||||
with:
|
||||
registry: ghcr.io
|
||||
username: ${{ github.repository_owner }}
|
||||
password: ${{ secrets.CR_PAT }}
|
||||
- name: Build base
|
||||
uses: docker/build-push-action@v2
|
||||
with:
|
||||
context: .
|
||||
file: ./docker/Dockerfile.base
|
||||
push: true
|
||||
tags: ghcr.io/lnis-uofu/openfpga-build-base:latest
|
||||
- name: Build environment image
|
||||
uses: docker/build-push-action@v2
|
||||
with:
|
||||
context: .
|
||||
file: ./docker/Dockerfile.env
|
||||
push: true
|
||||
tags: ghcr.io/lnis-uofu/openfpga-env:latest
|
||||
compiler_images:
|
||||
name: Build ${{ matrix.compiler }} compiler image
|
||||
needs: base_images
|
||||
runs-on: ubuntu-latest
|
||||
strategy:
|
||||
matrix:
|
||||
compiler:
|
||||
- gcc-5
|
||||
- gcc-6
|
||||
- gcc-7
|
||||
- gcc-8
|
||||
- gcc-9
|
||||
- clang-6.0
|
||||
- clang-8
|
||||
steps:
|
||||
- name: Checkout
|
||||
uses: actions/checkout@v2
|
||||
- name: Set up QEMU
|
||||
uses: docker/setup-qemu-action@v1
|
||||
- name: Set up Docker Buildx
|
||||
uses: docker/setup-buildx-action@v1
|
||||
- name: Login to GitHub Container Registry
|
||||
uses: docker/login-action@v1
|
||||
with:
|
||||
registry: ghcr.io
|
||||
username: ${{ github.repository_owner }}
|
||||
password: ${{ secrets.CR_PAT }}
|
||||
- name: Build ${{ matrix.compiler }} image
|
||||
uses: docker/build-push-action@v2
|
||||
with:
|
||||
context: .
|
||||
file: ./docker/Dockerfile.${{ matrix.compiler }}
|
||||
push: true
|
||||
tags: ghcr.io/lnis-uofu/openfpga-build-${{ matrix.compiler }}:latest
|
||||
|
|
@ -1,21 +1,22 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "FPGA-Bitstream regression tests";
|
||||
|
||||
echo -e "Testing bitstream generation for an auto-sized device";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
|
||||
|
||||
|
||||
echo -e "Testing bitstream generation for an 48x48 FPGA device";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing bitstream generation for an 96x96 FPGA device";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
|
||||
run-task fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing loading architecture bitstream from an external file";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
|
||||
run-task fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -1,11 +1,12 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "FPGA-SDC regression tests";
|
||||
|
||||
echo -e "Testing SDC generation with time units";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -1,11 +1,12 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "FPGA-SPICE regression tests";
|
||||
|
||||
echo -e "Testing FPGA-SPICE with netlist generation";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
|
||||
run-task fpga_spice/generate_spice --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -1,121 +1,121 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "FPGA-Verilog Feature Tests";
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
|
||||
run-task fpga_verilog/untileable --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with hard adder chain in CLBs ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
|
||||
run-task fpga_verilog/hard_adder --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with 16k block RAMs ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/reduced_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/embedded_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/soc_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with registerable I/Os for an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/registerable_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/registerable_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with adder chain across an FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with shift register chain across an FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with scan chain across an FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without buffers";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with behavioral description";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing implicit Verilog generation";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/implicit_verilog --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with flatten routing modules";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
|
||||
run-task fpga_verilog/flatten_routing --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with duplicated grid output pins";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
|
||||
run-task fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with spy output pads";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
|
||||
|
||||
run-task fpga_verilog/spypad --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Power-gating designs";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
|
||||
run-task fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
|
||||
|
||||
echo -e "Testing Depopulated crossbar in local routing";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/depopulate_crossbar --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Fully connected output crossbar in local routing";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing through channels in tileable routing";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
|
||||
|
||||
# Verify MCNC big20 benchmark suite with ModelSim
|
||||
# Verify MCNC big20 benchmark suite with ModelSim
|
||||
# Please make sure you have ModelSim installed in the environment
|
||||
# Otherwise, it will fail
|
||||
#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
|
||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
||||
#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
|
||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
apt-get update && apt-get install -y \
|
||||
autoconf \
|
||||
automake \
|
||||
bison \
|
||||
ccache \
|
||||
cmake \
|
||||
ctags \
|
||||
curl \
|
||||
doxygen \
|
||||
flex \
|
||||
fontconfig \
|
||||
gdb \
|
||||
git \
|
||||
gperf \
|
||||
iverilog \
|
||||
libc6-dev \
|
||||
libcairo2-dev \
|
||||
libevent-dev \
|
||||
libffi-dev \
|
||||
libfontconfig1-dev \
|
||||
liblist-moreutils-perl \
|
||||
libncurses5-dev \
|
||||
libreadline-dev \
|
||||
libx11-dev \
|
||||
libxft-dev \
|
||||
libxml++2.6-dev \
|
||||
make \
|
||||
perl \
|
||||
pkg-config \
|
||||
python3 \
|
||||
python3-setuptools \
|
||||
python3-lxml \
|
||||
python3-pip \
|
||||
qt5-default \
|
||||
tcllib \
|
||||
tcl8.6-dev \
|
||||
texinfo \
|
||||
time \
|
||||
valgrind \
|
||||
zip
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
apt-get install --no-install-recommends -y \
|
||||
libdatetime-perl libc6 libffi6 libgcc1 libreadline7 libstdc++6 \
|
||||
libtcl8.6 python3.8 python3-pip zlib1g libbz2-1.0 \
|
||||
iverilog git rsync make curl
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
name: "Pull Request Labeler"
|
||||
on:
|
||||
- pull_request_target
|
||||
- pull_request_target
|
||||
|
||||
jobs:
|
||||
triage:
|
||||
|
|
|
|||
|
|
@ -46,3 +46,5 @@ build/
|
|||
|
||||
message.txt
|
||||
deploy_key
|
||||
openfpga/openfpga
|
||||
vpr/vpr
|
||||
|
|
|
|||
194
.travis.yml
194
.travis.yml
|
|
@ -1,194 +0,0 @@
|
|||
language: cpp
|
||||
|
||||
# cache results
|
||||
|
||||
cache:
|
||||
directories:
|
||||
- $TRAVIS_BUILD_DIR/abc
|
||||
- $TRAVIS_BUILD_DIR/yosys
|
||||
- $TRAVIS_BUILD_DIR/ace2
|
||||
# - $TRAVIS_BUILD_DIR/libs
|
||||
- $HOME/.ccache
|
||||
# - $HOME/deps
|
||||
|
||||
# Currently sudo is not required, NO ENV is used
|
||||
|
||||
# Supported Operating systems
|
||||
dist: bionic
|
||||
#compiler: g++-8
|
||||
addons:
|
||||
apt:
|
||||
sources:
|
||||
- ubuntu-toolchain-r-test # For newer GCC
|
||||
- llvm_toolchain-trusty-7
|
||||
packages:
|
||||
- autoconf
|
||||
- automake
|
||||
- bash
|
||||
- bison
|
||||
- build-essential
|
||||
- cmake
|
||||
- ctags
|
||||
- curl
|
||||
- doxygen
|
||||
- flex
|
||||
- fontconfig
|
||||
- gdb
|
||||
- git
|
||||
- gperf
|
||||
- iverilog
|
||||
- libcairo2-dev
|
||||
- libevent-dev
|
||||
- libfontconfig1-dev
|
||||
- liblist-moreutils-perl
|
||||
- libncurses5-dev
|
||||
- libx11-dev
|
||||
- libxft-dev
|
||||
- libxml++2.6-dev
|
||||
- perl
|
||||
- python
|
||||
- python-lxml
|
||||
- texinfo
|
||||
- time
|
||||
- valgrind
|
||||
- zip
|
||||
- qt5-default
|
||||
- clang-format-7
|
||||
# Add all the supported compilers
|
||||
- g++-5
|
||||
- gcc-5
|
||||
- g++-6
|
||||
- gcc-6
|
||||
- g++-7
|
||||
- gcc-7
|
||||
- g++-8
|
||||
- gcc-8
|
||||
- g++-9
|
||||
- gcc-9
|
||||
- clang-6.0
|
||||
- clang-8
|
||||
#- os: osx
|
||||
# osx_image: xcode10.2 # we target latest MacOS Mojave
|
||||
# sudo: true
|
||||
# compiler: gcc-4.9 # Use clang instead of gcc in MacOS
|
||||
# addons:
|
||||
# homebrew:
|
||||
# packages:
|
||||
# - bison
|
||||
# - cmake
|
||||
# - ctags
|
||||
# - flex
|
||||
# - fontconfig
|
||||
# - git
|
||||
# - gcc@6
|
||||
# - gcc@4.9
|
||||
# - gawk
|
||||
# - icarus-verilog
|
||||
# - libxml++
|
||||
# - qt5
|
||||
|
||||
# Use gcc-8 as default compiler
|
||||
env:
|
||||
- MATRIX_EVAL="CC=gcc-8 && CXX=g++-8"
|
||||
|
||||
before_script:
|
||||
- source .travis/common.sh
|
||||
- source .travis/install.sh
|
||||
|
||||
stages:
|
||||
- name: Test
|
||||
if: type != cron
|
||||
|
||||
jobs:
|
||||
include:
|
||||
- stage: Test
|
||||
name: "Basic regression tests"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
- source .travis/basic_reg_test.sh
|
||||
|
||||
- stage: Test
|
||||
name: "FPGA-Verilog regression tests"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
- source .travis/fpga_verilog_reg_test.sh
|
||||
|
||||
- stage: Test
|
||||
name: "FPGA-Bitstream regression tests"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
- source .travis/fpga_bitstream_reg_test.sh
|
||||
|
||||
- stage: Test
|
||||
name: "FPGA-SDC regression tests"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
- source .travis/fpga_sdc_reg_test.sh
|
||||
|
||||
- stage: Test
|
||||
name: "FPGA-SPICE regression tests"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
- source .travis/fpga_spice_reg_test.sh
|
||||
|
||||
- stage: Test
|
||||
name: "Build Compatibility: GCC-5 (Ubuntu Bionic 18.04)"
|
||||
env:
|
||||
- MATRIX_EVAL="CC=gcc-5 && CXX=g++-5"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
|
||||
- stage: Test
|
||||
name: "Build Compatibility: GCC-6 (Ubuntu Bionic 18.04)"
|
||||
env:
|
||||
- MATRIX_EVAL="CC=gcc-6 && CXX=g++-6"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
|
||||
- stage: Test
|
||||
name: "Build Compatibility: GCC-7 (Ubuntu Bionic 18.04)"
|
||||
env:
|
||||
- MATRIX_EVAL="CC=gcc-7 && CXX=g++-7"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
|
||||
- stage: Test
|
||||
name: "Build Compatibility: GCC-8 (Ubuntu Bionic 18.04)"
|
||||
env:
|
||||
- MATRIX_EVAL="CC=gcc-8 && CXX=g++-8"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
|
||||
- stage: Test
|
||||
name: "Build Compatibility: GCC-9 (Ubuntu Bionic 18.04)"
|
||||
env:
|
||||
- MATRIX_EVAL="CC=gcc-9 && CXX=g++-9"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
|
||||
- stage: Test
|
||||
name: "Build Compatibility: Clang-6 (Ubuntu Bionic 18.04)"
|
||||
env:
|
||||
- MATRIX_EVAL="CC=clang-6.0 && CXX=clang++-6.0"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
|
||||
- stage: Test
|
||||
name: "Build Compatibility: Clang-8 (Ubuntu Bionic 18.04)"
|
||||
env:
|
||||
- MATRIX_EVAL="CC=clang-8 && CXX=clang++-8"
|
||||
script:
|
||||
- source .travis/build.sh
|
||||
|
||||
#after_failure:
|
||||
# - .travis/after_failure.sh
|
||||
|
||||
#after_success:
|
||||
# - .travis/after_success.sh
|
||||
|
||||
script:
|
||||
- true
|
||||
|
||||
notifications:
|
||||
slack:
|
||||
secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
source .travis/common.sh
|
||||
set -e
|
||||
|
||||
# Close the after_success.1 fold travis has created already.
|
||||
travis_time_finish
|
||||
travis_fold end after_failure.1
|
||||
|
||||
start_section "failure.tail" "${RED}Failure output...${NC}"
|
||||
tail -n 1000 output.log
|
||||
echo "Failed uploading files to LNIS Server"
|
||||
scp -qCr $TRAVIS_BUILD_DIR/openfpga_flow/tasks/ u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/
|
||||
scp output.log u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/
|
||||
end_section "failure.tail"
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
source .travis/common.sh
|
||||
set -e
|
||||
|
||||
# Close the after_success fold travis has created already.
|
||||
travis_fold end after_success
|
||||
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
|
||||
cd ${TRAVIS_BUILD_DIR}
|
||||
|
||||
source .github/workflows/basic_reg_test.sh
|
||||
|
||||
end_section "OpenFPGA.TaskTun"
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
source .travis/common.sh
|
||||
set -e
|
||||
|
||||
start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
|
||||
cd ${TRAVIS_BUILD_DIR}
|
||||
mkdir build
|
||||
cd build
|
||||
|
||||
if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
|
||||
cmake .. -DENABLE_VPR_GRAPHICS=off
|
||||
else
|
||||
cmake ..
|
||||
fi
|
||||
make -j16
|
||||
|
||||
# Return to upper directory
|
||||
cd ${TRAVIS_BUILD_DIR}
|
||||
|
||||
end_section "OpenFPGA.build"
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
# Some colors, use it like following;
|
||||
# echo -e "Hello ${YELLOW}yellow${NC}"
|
||||
GRAY='\033[0;30m'
|
||||
RED='\033[0;31m'
|
||||
GREEN='\033[0;32m'
|
||||
YELLOW='\033[0;33m'
|
||||
PURPLE='\033[0;35m'
|
||||
NC='\033[0m' # No Color
|
||||
|
||||
SPACER="echo -e ${GRAY} - ${NC}"
|
||||
|
||||
export -f travis_nanoseconds
|
||||
export -f travis_fold
|
||||
export -f travis_time_start
|
||||
export -f travis_time_finish
|
||||
|
||||
function start_section() {
|
||||
$SPACER
|
||||
travis_fold start "$1"
|
||||
travis_time_start
|
||||
echo -e "${PURPLE}OpenFPGA${NC}: - $2${NC}"
|
||||
echo -e "${GRAY}-------------------------------------------------------------------${NC}"
|
||||
}
|
||||
|
||||
function end_section() {
|
||||
echo -e "${GRAY}-------------------------------------------------------------------${NC}"
|
||||
travis_time_finish
|
||||
travis_fold end "$1"
|
||||
$SPACER
|
||||
}
|
||||
|
||||
# For Mac OS, we use g++ and gcc as default compilers
|
||||
if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
|
||||
export CC=gcc-4.9
|
||||
export CXX=g++-4.9
|
||||
# export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH"
|
||||
# export PATH="/usr/local/opt/qt/bin:$PATH"
|
||||
# Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h
|
||||
sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted
|
||||
else
|
||||
# For linux, we use g++-8 and gcc-8 as default compilers
|
||||
eval "${MATRIX_EVAL}"
|
||||
export "CC=$CC"
|
||||
export "CXX=$CXX"
|
||||
fi
|
||||
|
||||
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
|
||||
cd ${TRAVIS_BUILD_DIR}
|
||||
|
||||
source .github/workflows/fpga_bitstream_reg_test.sh
|
||||
|
||||
end_section "OpenFPGA.TaskTun"
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
|
||||
cd ${TRAVIS_BUILD_DIR}
|
||||
|
||||
source .github/workflows/fpga_sdc_reg_test.sh
|
||||
|
||||
end_section "OpenFPGA.TaskTun"
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
|
||||
cd ${TRAVIS_BUILD_DIR}
|
||||
|
||||
source .github/workflows/fpga_spice_reg_test.sh
|
||||
|
||||
end_section "OpenFPGA.TaskTun"
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
|
||||
cd ${TRAVIS_BUILD_DIR}
|
||||
|
||||
source .github/workflows/fpga_verilog_reg_test.sh
|
||||
|
||||
end_section "OpenFPGA.TaskTun"
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
source .travis/common.sh
|
||||
set -e
|
||||
|
||||
## Install necessary package which is not available on Travis CI
|
||||
export DEPS_DIR="${HOME}/deps"
|
||||
mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
|
||||
# Install CMake
|
||||
if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
|
||||
export CMAKE_URL="https://cmake.org/files/v3.16/cmake-3.16.3-Linux-x86_64.tar.gz"
|
||||
mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
|
||||
export PATH=${DEPS_DIR}/cmake/bin:${PATH}
|
||||
echo ${PATH}
|
||||
else
|
||||
brew install cmake || brew upgrade cmake
|
||||
fi
|
||||
cmake --version
|
||||
cd -
|
||||
#
|
||||
## Install latest iVerilog. Since no deb is provided, compile from source codes
|
||||
#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
|
||||
# export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz"
|
||||
# travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL}
|
||||
# mkdir -p iverilog-10_3
|
||||
# tar -xz v10_3.tar.gz
|
||||
# cd iverlog-10_3
|
||||
# sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin
|
||||
# ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin
|
||||
# make -j4
|
||||
# make check
|
||||
# make install --prefix=${HOME}/iverilog-10_3/bin
|
||||
# export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH}
|
||||
# echo ${PATH}
|
||||
#fi
|
||||
iverilog -V
|
||||
vvp -V
|
||||
#cd -
|
||||
|
||||
|
||||
# Git repo fixup
|
||||
#start_section "environment.git" "Setting up ${YELLOW}git checkout${NC}"
|
||||
#set -x
|
||||
#git fetch --tags
|
||||
#git submodule update --recursive --init
|
||||
#git submodule foreach git submodule update --recursive --init
|
||||
#set +x
|
||||
#end_section "environment.git"
|
||||
|
||||
$SPACER
|
||||
|
||||
24
Dockerfile
24
Dockerfile
|
|
@ -1,24 +0,0 @@
|
|||
FROM ubuntu:18.04
|
||||
ENV DEBIAN_FRONTEND=noninteractive
|
||||
RUN apt-get update && apt-get install -y clang \
|
||||
bison \
|
||||
flex \
|
||||
libreadline-dev \
|
||||
gawk \
|
||||
tcl-dev \
|
||||
libffi-dev \
|
||||
git \
|
||||
pkg-config \
|
||||
python3
|
||||
|
||||
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
|
||||
|
||||
RUN mkdir -p /release /dev
|
||||
|
||||
RUN cd release && git clone --single-branch --branch master https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
|
||||
|
||||
RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -DCMAKE_NO_GRAPHICS=on && make
|
||||
|
||||
RUN rm -rf /var/lib/apt/lists/*
|
||||
|
||||
WORKDIR /release/OpenFPGA
|
||||
BIN
deploy_key.enc
BIN
deploy_key.enc
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
FROM ubuntu:18.04
|
||||
ENV DEBIAN_FRONTEND=noninteractive
|
||||
RUN apt-get update && apt-get install software-properties-common -y
|
||||
# 18.04 includes 2.17 but github requires 2.18+ to support submodules.
|
||||
RUN add-apt-repository ppa:git-core/ppa
|
||||
ADD .github/workflows/install_dependencies_build.sh install_dependencies_build.sh
|
||||
RUN bash install_dependencies_build.sh
|
||||
ADD requirements.txt requirements.txt
|
||||
RUN python3 -m pip install -r requirements.txt
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-build-base
|
||||
RUN apt-get update && apt-get install -y clang-format-7 clang-6.0
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-build-base
|
||||
RUN apt-get update && apt-get install -y clang-format-7 clang-8
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
FROM ubuntu:18.04
|
||||
ENV DEBIAN_FRONTEND=noninteractive
|
||||
RUN apt-get update && apt-get install --no-install-recommends software-properties-common -y
|
||||
# 18.04 includes 2.17 but github requires 2.18+ to support submodules.
|
||||
RUN add-apt-repository ppa:git-core/ppa
|
||||
ADD .github/workflows/install_dependencies_run.sh install_dependencies_run.sh
|
||||
RUN bash install_dependencies_run.sh
|
||||
RUN curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py
|
||||
RUN python3.8 get-pip.py && rm get-pip.py
|
||||
RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.8 2
|
||||
RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.6 1
|
||||
ADD requirements.txt requirements.txt
|
||||
ENV PYTHON_EXEC=python3.8
|
||||
RUN ${PYTHON_EXEC} -m pip install -r requirements.txt
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-build-base
|
||||
RUN apt-get update && apt-get install -y gcc-5 g++-5
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-build-base
|
||||
RUN apt-get update && apt-get install -y gcc-6 g++-6
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-build-base
|
||||
RUN apt-get update && apt-get install -y gcc-7 g++-7
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-build-base
|
||||
RUN apt-get update && apt-get install -y gcc-8 g++-8
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-build-base
|
||||
RUN apt-get install -y software-properties-common
|
||||
RUN add-apt-repository ppa:ubuntu-toolchain-r/test
|
||||
RUN apt-get update && apt-get install -y gcc-9 g++-9
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
FROM ghcr.io/lnis-uofu/openfpga-env
|
||||
RUN mkdir -p /opt/openfpga
|
||||
WORKDIR /opt/openfpga
|
||||
COPY . /opt/openfpga
|
||||
RUN chmod +x abc/abc ace2/ace openfpga/openfpga vpr/vpr
|
||||
RUN chmod +x yosys/yosys yosys/yosys-abc yosys/yosys-config yosys/yosys-filterlib yosys/yosys-smtbmc
|
||||
ENV PATH="/opt/openfpga/openfpga:/opt/openfpga/yosys:${PATH}"
|
||||
ENV PATH="/opt/openfpga/ace2:/opt/openfpga/abc:/opt/openfpga/vpr:${PATH}"
|
||||
ENV OPENFPGA_PATH="/opt/openfpga"
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
|
||||
CI/CD setup
|
||||
------------
|
||||
|
||||
OpenFPGA implements CI/CD system using Github actions.
|
||||
The following figure shows the Actions implements flow.
|
||||
The source building is skipped if there are changes only in ``openfpga_flow`` or ``docs`` directory,
|
||||
in which case the docker image compiled for the latest master branch is used for running a regression.
|
||||
|
||||
|
||||
.. graphviz::
|
||||
:align: center
|
||||
|
||||
digraph G {
|
||||
node [fontname = "Handlee"];
|
||||
edge [fontname = "Handlee"];
|
||||
Trigger [
|
||||
label = "Action triggered"
|
||||
];
|
||||
|
||||
masterCompare [
|
||||
label = "Diff with current master"
|
||||
];
|
||||
|
||||
Build [
|
||||
label = "Changes only in\n openfpga_flow/doc?"
|
||||
shape = diamond
|
||||
];
|
||||
|
||||
BuildDocker [
|
||||
label = "Run build regression test\nBuild docker images"
|
||||
shape = box
|
||||
];
|
||||
|
||||
PushDockersCond [
|
||||
label = "Is merge\non master?"
|
||||
shape = diamond
|
||||
];
|
||||
|
||||
PushDockers [
|
||||
label = "Push docker Images\n(maintain compiled binary\nin docker + Example tasks)"
|
||||
shape = box
|
||||
];
|
||||
|
||||
RunRegression [
|
||||
label = "Run functional regeression test"
|
||||
shape = box
|
||||
];
|
||||
|
||||
Trigger ->masterCompare;
|
||||
masterCompare ->Build;
|
||||
Build -> BuildDocker [ label = "No" ];
|
||||
BuildDocker -> PushDockersCond;
|
||||
edge[weight=0.5] Build -> RunRegression [ label = "Yes" ];
|
||||
edge[weight=10] PushDockersCond -> RunRegression [ label = "No" ];
|
||||
PushDockersCond -> PushDockers [ label = "Yes" ];
|
||||
edge[weight=2] PushDockers -> RunRegression;
|
||||
|
||||
{
|
||||
rank=same;
|
||||
PushDockersCond PushDockers;
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
|
|
||||
|
||||
|
||||
.. option:: Build regression test
|
||||
|
||||
The OpenFPGA soure is compiled with the following set of compilers.
|
||||
|
||||
#. gcc-5
|
||||
#. gcc-6
|
||||
#. gcc-7
|
||||
#. gcc-8
|
||||
#. gcc-9
|
||||
#. clang-6.0
|
||||
#. clang-8
|
||||
|
||||
The docker images for these build enviroment are available on `github packages <https://github.com/orgs/lnis-uofu/packages>`_.
|
||||
|
||||
.. option:: Functional regeression test
|
||||
|
||||
OpenFPGA maintains a set of functional tests to validate the different functionality.
|
||||
The test are broadly catagories into ``basic_reg_test``, ``fpga_verilog_reg_test``,
|
||||
``fpga_bitstream_reg_test``, ``fpga_sdc_reg_test``, and ``fpga_spice_reg_test``.
|
||||
A functional regression test is run for every commit on every branch.
|
||||
|
||||
|
||||
How to debug failed regression test
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
In case the ``funtional regression test`` fails,
|
||||
the actions script will collect all ``.log`` files from
|
||||
the task directory and upload as a artifacts on github storage.
|
||||
These artifacts can be downloaded from the github website actions tab, for more reference follow `this <https://docs.github.com/en/actions/managing-workflow-runs/downloading-workflow-artifacts>`_ article.
|
||||
|
||||
**NOTE** : The retention time of these artifacts is 1 day,
|
||||
so in case user want to reserve the failure log for longer duration back it up locally
|
||||
|
||||
Release Docker Images
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. option:: ghcr.io/lnis-uofu/openfpga-master:latest
|
||||
|
||||
This is a bleeding-edge release from the current master branch of OpenFPGA.
|
||||
It is updated automatically whenever there is activity on the master branch.
|
||||
Due to high development activity, we recommend the user to use the bleeding-edge version to get access to all new features and report an issue in case there are any bugs.
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
ci_cd_setup/index
|
||||
|
|
@ -24,6 +24,12 @@ Welcome to OpenFPGA's documentation!
|
|||
|
||||
manual/index
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
:caption: Developers Manual
|
||||
|
||||
dev_manual/index
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
:caption: Appendix
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ Template
|
|||
Configuration Chain Example
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
The following XML code describes a scan-chain circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_ccff_fpga`.
|
||||
It will use the circuit model defined in :numref:`fig_ccff`.
|
||||
It will use the circuit model defined in :numref:`fig_ccff_config_chain`.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
|
|
|
|||
|
|
@ -27,151 +27,4 @@ A fabric key can be achieved in the following ways:
|
|||
File Format
|
||||
```````````
|
||||
|
||||
A fabric key follows an XML format. As shown in the following XML code, the key file includes the organization of configurable blocks in the top-level FPGA fabric.
|
||||
|
||||
Configurable Region
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The top-level FPGA fabric can consist of several configurable regions, where a region may contain one or multiple configurable blocks. Each configurable region can be configured independently and in parrallel.
|
||||
|
||||
.. option:: <region id="<int>"/>
|
||||
|
||||
- ``id`` indicates the unique id of a configurable region in the fabric.
|
||||
|
||||
.. warning:: The id must start from zero!
|
||||
|
||||
.. note:: The number of regions defined in the fabric key must be consistent with the number of regions defined in the configuration protocol of architecture description. (See details in :ref:`config_protocol`).
|
||||
|
||||
The following example shows how to define multiple configuration regions in the fabric key.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<fabric_key>
|
||||
<region id="0">
|
||||
<key id="0" name="grid_io_bottom" value="0" alias="grid_io_bottom_1__0_"/>
|
||||
<key id="1" name="grid_io_right" value="0" alias="grid_io_right_2__1_"/>
|
||||
<key id="2" name="sb_1__1_" value="0" alias="sb_1__1_"/>
|
||||
</region>
|
||||
<region id="1">
|
||||
<key id="3" name="cbx_1__1_" value="0" alias="cbx_1__1_"/>
|
||||
<key id="4" name="grid_io_top" value="0" alias="grid_io_top_1__2_"/>
|
||||
<key id="5" name="sb_0__1_" value="0" alias="sb_0__1_"/>
|
||||
</region>
|
||||
<region id="2">
|
||||
<key id="6" name="sb_0__0_" value="0" alias="sb_0__0_"/>
|
||||
<key id="7" name="cby_0__1_" value="0" alias="cby_0__1_"/>
|
||||
<key id="8" name="grid_io_left" value="0" alias="grid_io_left_0__1_"/>
|
||||
</region>
|
||||
<region id="3">
|
||||
<key id="9" name="sb_1__0_" value="0" alias="sb_1__0_"/>
|
||||
<key id="10" name="cbx_1__0_" value="0" alias="cbx_1__0_"/>
|
||||
<key id="11" name="cby_1__1_" value="0" alias="cby_1__1_"/>
|
||||
<key id="12" name="grid_clb" value="0" alias="grid_clb_1__1_"/>
|
||||
</region>
|
||||
</fabric_key>
|
||||
|
||||
|
||||
Configurable Block
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Each configurable block is defined as a key. There are two ways to define a key, either with alias or with name and value.
|
||||
|
||||
.. option:: <key id="<int>" alias="<string>" name="<string>" value="<int>"/>
|
||||
|
||||
- ``id`` indicates the sequence of the configurable memory block in the top-level FPGA fabric.
|
||||
|
||||
- ``name`` indicates the module name of the configurable memory block. This property becomes optional when ``alias`` is defined.
|
||||
|
||||
- ``value`` indicates the instance id of the configurable memory block in the top-level FPGA fabric. This property becomes optional when ``alias`` is defined.
|
||||
|
||||
- ``alias`` indicates the instance name of the configurable memory block in the top-level FPGA fabric. If a valid alias is specified, the ``name`` and ``value`` are not required.
|
||||
|
||||
.. warning:: For fast loading of fabric key, strongly recommend to use pairs ``name`` and ``alias`` or ``name`` and ``value`` in the fabric key file. Using only ``alias`` may cause long parsing time for fabric key.
|
||||
|
||||
The following is an example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA.
|
||||
This key contains only ``alias`` which is easy to craft.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<fabric_key>
|
||||
<region id="0">
|
||||
<key id="0" alias="sb_2__2_"/>
|
||||
<key id="1" alias="grid_clb_2_2"/>
|
||||
<key id="2" alias="sb_0__1_"/>
|
||||
<key id="3" alias="cby_0__1_"/>
|
||||
<key id="4" alias="grid_clb_2_1"/>
|
||||
<key id="5" alias="grid_io_left_0_1"/>
|
||||
<key id="6" alias="sb_1__0_"/>
|
||||
<key id="7" alias="sb_1__1_"/>
|
||||
<key id="8" alias="cbx_2__1_"/>
|
||||
<key id="9" alias="cby_1__2_"/>
|
||||
<key id="10" alias="grid_io_right_3_2"/>
|
||||
<key id="11" alias="cbx_2__0_"/>
|
||||
<key id="12" alias="cby_1__1_"/>
|
||||
<key id="13" alias="grid_io_right_3_1"/>
|
||||
<key id="14" alias="grid_io_bottom_1_0"/>
|
||||
<key id="15" alias="cby_2__1_"/>
|
||||
<key id="16" alias="sb_2__1_"/>
|
||||
<key id="17" alias="cbx_1__0_"/>
|
||||
<key id="18" alias="grid_clb_1_2"/>
|
||||
<key id="19" alias="cbx_1__2_"/>
|
||||
<key id="20" alias="cbx_2__2_"/>
|
||||
<key id="21" alias="sb_2__0_"/>
|
||||
<key id="22" alias="sb_1__2_"/>
|
||||
<key id="23" alias="cby_0__2_"/>
|
||||
<key id="24" alias="sb_0__0_"/>
|
||||
<key id="25" alias="grid_clb_1_1"/>
|
||||
<key id="26" alias="cby_2__2_"/>
|
||||
<key id="27" alias="grid_io_top_2_3"/>
|
||||
<key id="28" alias="sb_0__2_"/>
|
||||
<key id="29" alias="grid_io_bottom_2_0"/>
|
||||
<key id="30" alias="cbx_1__1_"/>
|
||||
<key id="31" alias="grid_io_top_1_3"/>
|
||||
<key id="32" alias="grid_io_left_0_2"/>
|
||||
</region>
|
||||
</fabric_key>
|
||||
|
||||
The following shows another example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA.
|
||||
This key contains only ``name`` and ``value`` which is fast to parse.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<fabric_key>
|
||||
<region id="0">
|
||||
<key id="0" name="sb_2__2_" value="0"/>
|
||||
<key id="1" name="grid_clb" value="3"/>
|
||||
<key id="2" name="sb_0__1_" value="0"/>
|
||||
<key id="3" name="cby_0__1_" value="0"/>
|
||||
<key id="4" name="grid_clb" value="2"/>
|
||||
<key id="5" name="grid_io_left" value="0"/>
|
||||
<key id="6" name="sb_1__0_" value="0"/>
|
||||
<key id="7" name="sb_1__1_" value="0"/>
|
||||
<key id="8" name="cbx_1__1_" value="1"/>
|
||||
<key id="9" name="cby_1__1_" value="1"/>
|
||||
<key id="10" name="grid_io_right" value="1"/>
|
||||
<key id="11" name="cbx_1__0_" value="1"/>
|
||||
<key id="12" name="cby_1__1_" value="0"/>
|
||||
<key id="13" name="grid_io_right" value="0"/>
|
||||
<key id="14" name="grid_io_bottom" value="0"/>
|
||||
<key id="15" name="cby_2__1_" value="0"/>
|
||||
<key id="16" name="sb_2__1_" value="0"/>
|
||||
<key id="17" name="cbx_1__0_" value="0"/>
|
||||
<key id="18" name="grid_clb" value="1"/>
|
||||
<key id="19" name="cbx_1__2_" value="0"/>
|
||||
<key id="20" name="cbx_1__2_" value="1"/>
|
||||
<key id="21" name="sb_2__0_" value="0"/>
|
||||
<key id="22" name="sb_1__2_" value="0"/>
|
||||
<key id="23" name="cby_0__1_" value="1"/>
|
||||
<key id="24" name="sb_0__0_" value="0"/>
|
||||
<key id="25" name="grid_clb" value="0"/>
|
||||
<key id="26" name="cby_2__1_" value="1"/>
|
||||
<key id="27" name="grid_io_top" value="1"/>
|
||||
<key id="28" name="sb_0__2_" value="0"/>
|
||||
<key id="29" name="grid_io_bottom" value="1"/>
|
||||
<key id="30" name="cbx_1__1_" value="0"/>
|
||||
<key id="31" name="grid_io_top" value="0"/>
|
||||
<key id="32" name="grid_io_left" value="1"/>
|
||||
</region>
|
||||
</fabric_key>
|
||||
|
||||
|
||||
See details in :ref:`file_formats_fabric_key`
|
||||
|
|
|
|||
|
|
@ -0,0 +1,100 @@
|
|||
.. _file_formats_architecture_bitstream:
|
||||
|
||||
Architecture Bitstream (.xml)
|
||||
-----------------------------
|
||||
|
||||
OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes the following information:
|
||||
|
||||
- ``name`` represents the instance name which you can find in the fabric netlists
|
||||
|
||||
- ``hierarchy_level`` represents the depth of this block in the hierarchy of the FPGA fabric. It always starts from 0 as the root.
|
||||
|
||||
- ``hierarchy`` represents the location of this block in FPGA fabric.
|
||||
The hierachy includes the full hierarchy of this block
|
||||
|
||||
- ``instance`` denotes the instance name which you can find in the fabric netlists
|
||||
|
||||
- ``level`` denotes the depth of the block in the hierarchy
|
||||
|
||||
- ``input_nets`` represents the path ids and net names that are mapped to the inputs of block. Unused inputs will be tagged as ``unmapped`` which is a reserved word of OpenFPGA. Path id corresponds the selected ``path_id`` in the ``<bitstream>`` node.
|
||||
|
||||
- ``output_nets`` represents the path ids and net names that are mapped to the outputs of block. Unused outputs will be tagged as ``unmapped`` which is a reserved word OpenFPGA.
|
||||
|
||||
- ``bitstream`` represents the configuration bits affiliated to this block.
|
||||
|
||||
- ``path_id`` denotes the index of inputs which is propagated to the output. Note that smallest valid index starts from zero. Only routing multiplexers have the path index. Unused routing multiplexer will not have a ``path_id`` of ``-1``, which allows bitstream assembler to freely find the best path in terms of Quality of Results (QoR). A used routing multiplexer should have a zero or positive ``path_id``.
|
||||
|
||||
- ``bit`` denotes a single configuration bit under this block. It contains \
|
||||
|
||||
- ``memory_port`` the memory port name which you can find in the fabric netlists by following the hierarchy.
|
||||
|
||||
- ``value`` a binary value which is the configuration bit assigned to the memory port.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bitstream_block name="fpga_top" hierarchy_level="0">
|
||||
<!-- Bitstream block of a 4-input Look-Up Table in a Configurable Logic Block (CLB) -->
|
||||
<bitstream_block name="grid_clb_1_1" hierarchy_level="1">
|
||||
<bitstream_block name="logical_tile_clb_mode_clb__0" hierarchy_level="2">
|
||||
<bitstream_block name="logical_tile_clb_mode_default__fle_0" hierarchy_level="3">
|
||||
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0" hierarchy_level="4">
|
||||
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0" hierarchy_level="5">
|
||||
<bitstream_block name="lut4_config_latch_mem" hierarchy_level="6">
|
||||
<hierarchy>
|
||||
<instance level="0" name="fpga_top"/>
|
||||
<instance level="1" name="grid_clb_1_1"/>
|
||||
<instance level="2" name="logical_tile_clb_mode_clb__0"/>
|
||||
<instance level="3" name="logical_tile_clb_mode_default__fle_0"/>
|
||||
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
|
||||
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0"/>
|
||||
<instance level="6" name="lut4_config_latch_mem"/>
|
||||
</hierarchy>
|
||||
<bitstream>
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[3]" value="0"/>
|
||||
<bit memory_port="mem_out[4]" value="0"/>
|
||||
<bit memory_port="mem_out[5]" value="0"/>
|
||||
<bit memory_port="mem_out[6]" value="0"/>
|
||||
<bit memory_port="mem_out[7]" value="0"/>
|
||||
<bit memory_port="mem_out[8]" value="0"/>
|
||||
<bit memory_port="mem_out[9]" value="0"/>
|
||||
<bit memory_port="mem_out[10]" value="0"/>
|
||||
<bit memory_port="mem_out[11]" value="0"/>
|
||||
<bit memory_port="mem_out[12]" value="0"/>
|
||||
<bit memory_port="mem_out[13]" value="0"/>
|
||||
<bit memory_port="mem_out[14]" value="0"/>
|
||||
<bit memory_port="mem_out[15]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
||||
<!-- More bitstream blocks -->
|
||||
|
||||
<!-- Bitstream block of a 2-input routing multiplexer in a Switch Block (SB) -->
|
||||
<bitstream_block name="sb_0__2_" hierarchy_level="1">
|
||||
<bitstream_block name="mem_right_track_0" hierarchy_level="2">
|
||||
<hierarchy>
|
||||
<instance level="0" name="fpga_top"/>
|
||||
<instance level="1" name="sb_0__2_"/>
|
||||
<instance level="2" name="mem_right_track_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
.. _file_formats_fabric_bitstream:
|
||||
|
||||
Fabric-dependent Bitstream
|
||||
--------------------------
|
||||
|
||||
.. _file_formats_fabric_bitstream_plain_text:
|
||||
|
||||
Plain text (.txt)
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
This file format is designed to be directly loaded to an FPGA fabric.
|
||||
It does not include any comments but only bitstream.
|
||||
|
||||
The information depends on the type of configuration procotol.
|
||||
|
||||
.. option:: vanilla
|
||||
|
||||
A line consisting of ``0`` | ``1``
|
||||
|
||||
.. option:: scan_chain
|
||||
|
||||
A line consisting of ``0`` | ``1``
|
||||
|
||||
.. option:: memory_bank
|
||||
|
||||
Multiple lines will be included, each of which is organized as <address><space><bit>.
|
||||
Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired.
|
||||
The first line represents the Bit-Line address and configuration bit.
|
||||
The second line represents the Word-Line address and configuration bit.
|
||||
For example
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bitline_address> <bit_value>
|
||||
<wordline_address> <bit_value>
|
||||
<bitline_address> <bit_value>
|
||||
<wordline_address> <bit_value>
|
||||
...
|
||||
<bitline_address> <bit_value>
|
||||
<wordline_address> <bit_value>
|
||||
|
||||
.. option:: frame_based
|
||||
|
||||
Multiple lines will be included, each of which is organized as <address><space><bit>.
|
||||
Note that the address may include don't care bit which is denoted as ``x``.
|
||||
OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches.
|
||||
For example
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<frame_address> <bit_value>
|
||||
<frame_address> <bit_value>
|
||||
...
|
||||
<frame_address> <bit_value>
|
||||
|
||||
|
||||
.. _file_formats_fabric_bitstream_xml:
|
||||
|
||||
XML (.xml)
|
||||
~~~~~~~~~~
|
||||
|
||||
This file format is designed to generate testbenches using external tools, e.g., CocoTB.
|
||||
|
||||
In principle, the file consist a number of XML node ``<bit>``, each bit contains the following attributes:
|
||||
|
||||
- ``id``: The unique id of the configuration bit in the fabric bitstream.
|
||||
|
||||
- ``value``: The configuration bit value.
|
||||
|
||||
- ``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric.
|
||||
|
||||
A quick example:
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
|
||||
</bit>
|
||||
|
||||
Other information may depend on the type of configuration procotol.
|
||||
|
||||
.. option:: memory_bank
|
||||
|
||||
- ``bl``: Bit line address information
|
||||
|
||||
- ``wl``: Word line address information
|
||||
|
||||
A quick example:
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
|
||||
<bl address="000000"/>
|
||||
<wl address="000000"/>
|
||||
</bit>
|
||||
|
||||
.. option:: frame_based
|
||||
|
||||
- ``frame``: frame address information
|
||||
|
||||
.. note:: Frame address may include don't care bit which is denoted as ``x``.
|
||||
|
||||
A quick example:
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
|
||||
<frame address="0001000x00000x01"/>
|
||||
</bit>
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
.. _file_formats_fabric_key:
|
||||
|
||||
Fabric Key (.xml)
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
A fabric key follows an XML format. As shown in the following XML code, the key file includes the organization of configurable blocks in the top-level FPGA fabric.
|
||||
|
||||
Configurable Region
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The top-level FPGA fabric can consist of several configurable regions, where a region may contain one or multiple configurable blocks. Each configurable region can be configured independently and in parrallel.
|
||||
|
||||
.. option:: <region id="<int>"/>
|
||||
|
||||
- ``id`` indicates the unique id of a configurable region in the fabric.
|
||||
|
||||
.. warning:: The id must start from zero!
|
||||
|
||||
.. note:: The number of regions defined in the fabric key must be consistent with the number of regions defined in the configuration protocol of architecture description. (See details in :ref:`config_protocol`).
|
||||
|
||||
The following example shows how to define multiple configuration regions in the fabric key.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<fabric_key>
|
||||
<region id="0">
|
||||
<key id="0" name="grid_io_bottom" value="0" alias="grid_io_bottom_1__0_"/>
|
||||
<key id="1" name="grid_io_right" value="0" alias="grid_io_right_2__1_"/>
|
||||
<key id="2" name="sb_1__1_" value="0" alias="sb_1__1_"/>
|
||||
</region>
|
||||
<region id="1">
|
||||
<key id="3" name="cbx_1__1_" value="0" alias="cbx_1__1_"/>
|
||||
<key id="4" name="grid_io_top" value="0" alias="grid_io_top_1__2_"/>
|
||||
<key id="5" name="sb_0__1_" value="0" alias="sb_0__1_"/>
|
||||
</region>
|
||||
<region id="2">
|
||||
<key id="6" name="sb_0__0_" value="0" alias="sb_0__0_"/>
|
||||
<key id="7" name="cby_0__1_" value="0" alias="cby_0__1_"/>
|
||||
<key id="8" name="grid_io_left" value="0" alias="grid_io_left_0__1_"/>
|
||||
</region>
|
||||
<region id="3">
|
||||
<key id="9" name="sb_1__0_" value="0" alias="sb_1__0_"/>
|
||||
<key id="10" name="cbx_1__0_" value="0" alias="cbx_1__0_"/>
|
||||
<key id="11" name="cby_1__1_" value="0" alias="cby_1__1_"/>
|
||||
<key id="12" name="grid_clb" value="0" alias="grid_clb_1__1_"/>
|
||||
</region>
|
||||
</fabric_key>
|
||||
|
||||
|
||||
Configurable Block
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Each configurable block is defined as a key. There are two ways to define a key, either with alias or with name and value.
|
||||
|
||||
.. option:: <key id="<int>" alias="<string>" name="<string>" value="<int>"/>
|
||||
|
||||
- ``id`` indicates the sequence of the configurable memory block in the top-level FPGA fabric.
|
||||
|
||||
- ``name`` indicates the module name of the configurable memory block. This property becomes optional when ``alias`` is defined.
|
||||
|
||||
- ``value`` indicates the instance id of the configurable memory block in the top-level FPGA fabric. This property becomes optional when ``alias`` is defined.
|
||||
|
||||
- ``alias`` indicates the instance name of the configurable memory block in the top-level FPGA fabric. If a valid alias is specified, the ``name`` and ``value`` are not required.
|
||||
|
||||
.. warning:: For fast loading of fabric key, strongly recommend to use pairs ``name`` and ``alias`` or ``name`` and ``value`` in the fabric key file. Using only ``alias`` may cause long parsing time for fabric key.
|
||||
|
||||
The following is an example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA.
|
||||
This key contains only ``alias`` which is easy to craft.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<fabric_key>
|
||||
<region id="0">
|
||||
<key id="0" alias="sb_2__2_"/>
|
||||
<key id="1" alias="grid_clb_2_2"/>
|
||||
<key id="2" alias="sb_0__1_"/>
|
||||
<key id="3" alias="cby_0__1_"/>
|
||||
<key id="4" alias="grid_clb_2_1"/>
|
||||
<key id="5" alias="grid_io_left_0_1"/>
|
||||
<key id="6" alias="sb_1__0_"/>
|
||||
<key id="7" alias="sb_1__1_"/>
|
||||
<key id="8" alias="cbx_2__1_"/>
|
||||
<key id="9" alias="cby_1__2_"/>
|
||||
<key id="10" alias="grid_io_right_3_2"/>
|
||||
<key id="11" alias="cbx_2__0_"/>
|
||||
<key id="12" alias="cby_1__1_"/>
|
||||
<key id="13" alias="grid_io_right_3_1"/>
|
||||
<key id="14" alias="grid_io_bottom_1_0"/>
|
||||
<key id="15" alias="cby_2__1_"/>
|
||||
<key id="16" alias="sb_2__1_"/>
|
||||
<key id="17" alias="cbx_1__0_"/>
|
||||
<key id="18" alias="grid_clb_1_2"/>
|
||||
<key id="19" alias="cbx_1__2_"/>
|
||||
<key id="20" alias="cbx_2__2_"/>
|
||||
<key id="21" alias="sb_2__0_"/>
|
||||
<key id="22" alias="sb_1__2_"/>
|
||||
<key id="23" alias="cby_0__2_"/>
|
||||
<key id="24" alias="sb_0__0_"/>
|
||||
<key id="25" alias="grid_clb_1_1"/>
|
||||
<key id="26" alias="cby_2__2_"/>
|
||||
<key id="27" alias="grid_io_top_2_3"/>
|
||||
<key id="28" alias="sb_0__2_"/>
|
||||
<key id="29" alias="grid_io_bottom_2_0"/>
|
||||
<key id="30" alias="cbx_1__1_"/>
|
||||
<key id="31" alias="grid_io_top_1_3"/>
|
||||
<key id="32" alias="grid_io_left_0_2"/>
|
||||
</region>
|
||||
</fabric_key>
|
||||
|
||||
The following shows another example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA.
|
||||
This key contains only ``name`` and ``value`` which is fast to parse.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<fabric_key>
|
||||
<region id="0">
|
||||
<key id="0" name="sb_2__2_" value="0"/>
|
||||
<key id="1" name="grid_clb" value="3"/>
|
||||
<key id="2" name="sb_0__1_" value="0"/>
|
||||
<key id="3" name="cby_0__1_" value="0"/>
|
||||
<key id="4" name="grid_clb" value="2"/>
|
||||
<key id="5" name="grid_io_left" value="0"/>
|
||||
<key id="6" name="sb_1__0_" value="0"/>
|
||||
<key id="7" name="sb_1__1_" value="0"/>
|
||||
<key id="8" name="cbx_1__1_" value="1"/>
|
||||
<key id="9" name="cby_1__1_" value="1"/>
|
||||
<key id="10" name="grid_io_right" value="1"/>
|
||||
<key id="11" name="cbx_1__0_" value="1"/>
|
||||
<key id="12" name="cby_1__1_" value="0"/>
|
||||
<key id="13" name="grid_io_right" value="0"/>
|
||||
<key id="14" name="grid_io_bottom" value="0"/>
|
||||
<key id="15" name="cby_2__1_" value="0"/>
|
||||
<key id="16" name="sb_2__1_" value="0"/>
|
||||
<key id="17" name="cbx_1__0_" value="0"/>
|
||||
<key id="18" name="grid_clb" value="1"/>
|
||||
<key id="19" name="cbx_1__2_" value="0"/>
|
||||
<key id="20" name="cbx_1__2_" value="1"/>
|
||||
<key id="21" name="sb_2__0_" value="0"/>
|
||||
<key id="22" name="sb_1__2_" value="0"/>
|
||||
<key id="23" name="cby_0__1_" value="1"/>
|
||||
<key id="24" name="sb_0__0_" value="0"/>
|
||||
<key id="25" name="grid_clb" value="0"/>
|
||||
<key id="26" name="cby_2__1_" value="1"/>
|
||||
<key id="27" name="grid_io_top" value="1"/>
|
||||
<key id="28" name="sb_0__2_" value="0"/>
|
||||
<key id="29" name="grid_io_bottom" value="1"/>
|
||||
<key id="30" name="cbx_1__1_" value="0"/>
|
||||
<key id="31" name="grid_io_top" value="0"/>
|
||||
<key id="32" name="grid_io_left" value="1"/>
|
||||
</region>
|
||||
</fabric_key>
|
||||
|
|
@ -12,3 +12,10 @@ OpenFPGA widely uses XML format for interchangable files
|
|||
|
||||
pin_constraints_file
|
||||
|
||||
repack_design_constraints
|
||||
|
||||
architecture_bitstream
|
||||
|
||||
fabric_bitstream
|
||||
|
||||
fabric_key
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
.. _file_format_pin_constraints_file:
|
||||
|
||||
Pin Constraints File
|
||||
--------------------
|
||||
Pin Constraints File (.xml)
|
||||
---------------------------
|
||||
|
||||
The *Pin Constraints File* (PCF) aims to create pin binding between an implementation and an FPGA fabric
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
.. _fpga_bitstream_repack_design_constraints:
|
||||
.. _file_formats_repack_design_constraints:
|
||||
|
||||
Repack Design Constraints
|
||||
-------------------------
|
||||
Repack Design Constraints (.xml)
|
||||
--------------------------------
|
||||
|
||||
An example of design constraints is shown as follows.
|
||||
|
||||
|
|
@ -13,98 +13,9 @@ The fabric bitsteam can be outputted in different file format in terms of usage.
|
|||
Plain Text File Format
|
||||
```````````````````````
|
||||
|
||||
This file format is designed to be directly loaded to an FPGA fabric.
|
||||
It does not include any comments but only bitstream.
|
||||
|
||||
The information depends on the type of configuration procotol.
|
||||
|
||||
.. option:: vanilla
|
||||
|
||||
A line consisting of ``0`` | ``1``
|
||||
|
||||
.. option:: scan_chain
|
||||
|
||||
A line consisting of ``0`` | ``1``
|
||||
|
||||
.. option:: memory_bank
|
||||
|
||||
Multiple lines will be included, each of which is organized as <address><space><bit>.
|
||||
Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired.
|
||||
The first line represents the Bit-Line address and configuration bit.
|
||||
The second line represents the Word-Line address and configuration bit.
|
||||
For example
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bitline_address> <bit_value>
|
||||
<wordline_address> <bit_value>
|
||||
<bitline_address> <bit_value>
|
||||
<wordline_address> <bit_value>
|
||||
...
|
||||
<bitline_address> <bit_value>
|
||||
<wordline_address> <bit_value>
|
||||
|
||||
.. option:: frame_based
|
||||
|
||||
Multiple lines will be included, each of which is organized as <address><space><bit>.
|
||||
Note that the address may include don't care bit which is denoted as ``x``.
|
||||
OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches.
|
||||
For example
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<frame_address> <bit_value>
|
||||
<frame_address> <bit_value>
|
||||
...
|
||||
<frame_address> <bit_value>
|
||||
See details in :ref:`file_formats_fabric_bitstream_plain_text`
|
||||
|
||||
XML File Format
|
||||
```````````````
|
||||
|
||||
This file format is designed to generate testbenches using external tools, e.g., CocoTB.
|
||||
|
||||
In principle, the file consist a number of XML node ``<bit>``, each bit contains the following attributes:
|
||||
|
||||
- ``id``: The unique id of the configuration bit in the fabric bitstream.
|
||||
|
||||
- ``value``: The configuration bit value.
|
||||
|
||||
- ``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric.
|
||||
|
||||
A quick example:
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
|
||||
</bit>
|
||||
|
||||
Other information may depend on the type of configuration procotol.
|
||||
|
||||
.. option:: memory_bank
|
||||
|
||||
- ``bl``: Bit line address information
|
||||
|
||||
- ``wl``: Word line address information
|
||||
|
||||
A quick example:
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
|
||||
<bl address="000000"/>
|
||||
<wl address="000000"/>
|
||||
</bit>
|
||||
|
||||
.. option:: frame_based
|
||||
|
||||
- ``frame``: frame address information
|
||||
|
||||
.. note:: Frame address may include don't care bit which is denoted as ``x``.
|
||||
|
||||
A quick example:
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
|
||||
<frame address="0001000x00000x01"/>
|
||||
</bit>
|
||||
See details in :ref:`file_formats_fabric_bitstream_xml`
|
||||
|
|
|
|||
|
|
@ -18,97 +18,4 @@ This can be regarded as a raw bitstream used for
|
|||
File Format
|
||||
```````````
|
||||
|
||||
OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes the following information:
|
||||
- ``name`` represents the instance name which you can find in the fabric netlists
|
||||
|
||||
- ``hierarchy_level`` represents the depth of this block in the hierarchy of the FPGA fabric. It always starts from 0 as the root.
|
||||
|
||||
- ``hierarchy`` represents the location of this block in FPGA fabric.
|
||||
The hierachy includes the full hierarchy of this block
|
||||
|
||||
- ``instance`` denotes the instance name which you can find in the fabric netlists
|
||||
|
||||
- ``level`` denotes the depth of the block in the hierarchy
|
||||
|
||||
- ``input_nets`` represents the path ids and net names that are mapped to the inputs of block. Unused inputs will be tagged as ``unmapped`` which is a reserved word of OpenFPGA. Path id corresponds the selected ``path_id`` in the ``<bitstream>`` node.
|
||||
|
||||
- ``output_nets`` represents the path ids and net names that are mapped to the outputs of block. Unused outputs will be tagged as ``unmapped`` which is a reserved word OpenFPGA.
|
||||
|
||||
- ``bitstream`` represents the configuration bits affiliated to this block.
|
||||
|
||||
- ``path_id`` denotes the index of inputs which is propagated to the output. Note that smallest valid index starts from zero. Only routing multiplexers have the path index. Unused routing multiplexer will not have a ``path_id`` of ``-1``, which allows bitstream assembler to freely find the best path in terms of Quality of Results (QoR). A used routing multiplexer should have a zero or positive ``path_id``.
|
||||
|
||||
- ``bit`` denotes a single configuration bit under this block. It contains \
|
||||
|
||||
- ``memory_port`` the memory port name which you can find in the fabric netlists by following the hierarchy.
|
||||
|
||||
- ``value`` a binary value which is the configuration bit assigned to the memory port.
|
||||
|
||||
.. code-block:: xml
|
||||
|
||||
<bitstream_block name="fpga_top" hierarchy_level="0">
|
||||
<!-- Bitstream block of a 4-input Look-Up Table in a Configurable Logic Block (CLB) -->
|
||||
<bitstream_block name="grid_clb_1_1" hierarchy_level="1">
|
||||
<bitstream_block name="logical_tile_clb_mode_clb__0" hierarchy_level="2">
|
||||
<bitstream_block name="logical_tile_clb_mode_default__fle_0" hierarchy_level="3">
|
||||
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0" hierarchy_level="4">
|
||||
<bitstream_block name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0" hierarchy_level="5">
|
||||
<bitstream_block name="lut4_config_latch_mem" hierarchy_level="6">
|
||||
<hierarchy>
|
||||
<instance level="0" name="fpga_top"/>
|
||||
<instance level="1" name="grid_clb_1_1"/>
|
||||
<instance level="2" name="logical_tile_clb_mode_clb__0"/>
|
||||
<instance level="3" name="logical_tile_clb_mode_default__fle_0"/>
|
||||
<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
|
||||
<instance level="5" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0"/>
|
||||
<instance level="6" name="lut4_config_latch_mem"/>
|
||||
</hierarchy>
|
||||
<bitstream>
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
<bit memory_port="mem_out[2]" value="0"/>
|
||||
<bit memory_port="mem_out[3]" value="0"/>
|
||||
<bit memory_port="mem_out[4]" value="0"/>
|
||||
<bit memory_port="mem_out[5]" value="0"/>
|
||||
<bit memory_port="mem_out[6]" value="0"/>
|
||||
<bit memory_port="mem_out[7]" value="0"/>
|
||||
<bit memory_port="mem_out[8]" value="0"/>
|
||||
<bit memory_port="mem_out[9]" value="0"/>
|
||||
<bit memory_port="mem_out[10]" value="0"/>
|
||||
<bit memory_port="mem_out[11]" value="0"/>
|
||||
<bit memory_port="mem_out[12]" value="0"/>
|
||||
<bit memory_port="mem_out[13]" value="0"/>
|
||||
<bit memory_port="mem_out[14]" value="0"/>
|
||||
<bit memory_port="mem_out[15]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
|
||||
<!-- More bitstream blocks -->
|
||||
|
||||
<!-- Bitstream block of a 2-input routing multiplexer in a Switch Block (SB) -->
|
||||
<bitstream_block name="sb_0__2_" hierarchy_level="1">
|
||||
<bitstream_block name="mem_right_track_0" hierarchy_level="2">
|
||||
<hierarchy>
|
||||
<instance level="0" name="fpga_top"/>
|
||||
<instance level="1" name="sb_0__2_"/>
|
||||
<instance level="2" name="mem_right_track_0"/>
|
||||
</hierarchy>
|
||||
<input_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
<path id="1" net_name="unmapped"/>
|
||||
</input_nets>
|
||||
<output_nets>
|
||||
<path id="0" net_name="unmapped"/>
|
||||
</output_nets>
|
||||
<bitstream path_id="-1">
|
||||
<bit memory_port="mem_out[0]" value="0"/>
|
||||
<bit memory_port="mem_out[1]" value="0"/>
|
||||
</bitstream>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
</bitstream_block>
|
||||
See details in :ref:`file_formats_architecture_bitstream`
|
||||
|
|
|
|||
|
|
@ -12,5 +12,3 @@ FPGA-Bitstream can generate two types of bitstreams:
|
|||
generic_bitstream
|
||||
|
||||
fabric_dependent_bitstream
|
||||
|
||||
repack_design_constraints
|
||||
|
|
|
|||
|
|
@ -15,6 +15,17 @@ To launch OpenFPGA shell, users can choose two modes.
|
|||
|
||||
Launch OpenFPGA in script mode where users write commands in scripts and FPGA will execute them
|
||||
|
||||
.. option:: --batch_execution or -batch
|
||||
|
||||
Execute OpenFPGA script in batch mode. This option is only valid for script mode.
|
||||
|
||||
- If in batch mode, OpenFPGA will abort immediately when fatal errors occurred.
|
||||
- If not in batch mode, OpenFPGA will enter interactive mode when fatal errors occurred.
|
||||
|
||||
.. option:: --version or -v
|
||||
|
||||
Print version information of OpenFPGA
|
||||
|
||||
.. option:: --help or -h
|
||||
|
||||
Show the help desk
|
||||
|
|
|
|||
|
|
@ -3,6 +3,11 @@
|
|||
Basic Commands
|
||||
--------------
|
||||
|
||||
version
|
||||
~~~~~~~
|
||||
|
||||
Show OpenFPGA version information
|
||||
|
||||
help
|
||||
~~~~
|
||||
|
||||
|
|
|
|||
|
|
@ -14,46 +14,61 @@ Repack's functionality are in the following aspects:
|
|||
|
||||
- It re-routes all the nets by considering the programmable interconnects in physical modes **only**.
|
||||
|
||||
.. note:: This must be done before bitstream generator and testbench generation. Strongly recommend it is done after all the fix-up have been applied
|
||||
.. note:: This must be done before bitstream generator and testbench generation. Strongly recommend it is done after all the fix-up have been applied
|
||||
|
||||
.. option:: --design_constraints
|
||||
|
||||
Apply design constraints from an external file.
|
||||
Normally, repack takes the net mapping from VPR packing and routing results.
|
||||
Alternatively, repack can accept the design constraints, in particular, net remapping, from an XML-based design constraint description.
|
||||
See details in :ref:`fpga_bitstream_repack_design_constraints`.
|
||||
|
||||
.. warning:: Design constraints are designed to help repacker to identify which clock net to be mapped to which pin, so that multi-clock benchmarks can be correctly implemented, in the case that VPR may not have sufficient vision on clock net mapping. **Try not to use design constraints to remap any other types of nets!!!**
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
.. option:: --design_constraints
|
||||
|
||||
Apply design constraints from an external file.
|
||||
Normally, repack takes the net mapping from VPR packing and routing results.
|
||||
Alternatively, repack can accept the design constraints, in particular, net remapping, from an XML-based design constraint description.
|
||||
See details in :ref:`file_formats_repack_design_constraints`.
|
||||
|
||||
.. warning:: Design constraints are designed to help repacker to identify which clock net to be mapped to which pin, so that multi-clock benchmarks can be correctly implemented, in the case that VPR may not have sufficient vision on clock net mapping. **Try not to use design constraints to remap any other types of nets!!!**
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
build_architecture_bitstream
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Decode VPR implementing results to an fabric-independent bitstream database
|
||||
|
||||
- ``--read_file`` Read the fabric-independent bitstream from an XML file. When this is enabled, bitstream generation will NOT consider VPR results.
|
||||
.. option:: --read_file <string>
|
||||
|
||||
- ``--write_file`` Output the fabric-independent bitstream to an XML file
|
||||
Read the fabric-independent bitstream from an XML file. When this is enabled, bitstream generation will NOT consider VPR results. See details at :ref:`file_formats_architecture_bitstream`.
|
||||
|
||||
.. option:: --write_file <string>
|
||||
|
||||
Output the fabric-independent bitstream to an XML file. See details at :ref:`file_formats_architecture_bitstream`.
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
build_fabric_bitstream
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
write_fabric_bitstream
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Output the fabric bitstream database to a specific file format
|
||||
|
||||
- ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1)
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
- ``--format`` Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``.
|
||||
Output the fabric bitstream to an plain text file (only ``0`` or ``1``)
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --format <string>
|
||||
|
||||
Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``.
|
||||
See file formats in :ref:`file_formats_fabric_bitstream_xml` and :ref:`file_formats_fabric_bitstream_plain_text`.
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
|
|
|||
|
|
@ -8,77 +8,127 @@ write_pnr_sdc
|
|||
|
||||
Write the SDC files for PnR backend
|
||||
|
||||
- ``--file`` or ``-f`` Specify the output directory for SDC files
|
||||
|
||||
- ``--hierarchical`` Output SDC files without full path in hierarchy
|
||||
|
||||
- ``--flatten_names`` Use flatten names (no wildcards) in SDC files
|
||||
|
||||
- ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
|
||||
|
||||
- ``--output_hierarchy`` Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks.
|
||||
|
||||
.. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric``
|
||||
|
||||
- ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.
|
||||
|
||||
- ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric
|
||||
|
||||
.. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well.
|
||||
|
||||
- ``--constrain_grid`` Constrain all the grids of FPGA fabric
|
||||
|
||||
- ``--constrain_sb`` Constrain all the switch blocks of FPGA fabric
|
||||
|
||||
- ``--constrain_cb`` Constrain all the connection blocks of FPGA fabric
|
||||
|
||||
- ``--constrain_configurable_memory_outputs`` Constrain all the outputs of configurable memories of FPGA fabric
|
||||
|
||||
- ``--constrain_routing_multiplexer_outputs`` Constrain all the outputs of routing multiplexer of FPGA fabric
|
||||
|
||||
- ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric
|
||||
|
||||
- ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric
|
||||
|
||||
.. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
Specify the output directory for SDC files
|
||||
For example, ``--file /temp/pnr_sdc``
|
||||
|
||||
.. option:: --hierarchical
|
||||
|
||||
Output SDC files without full path in hierarchy
|
||||
|
||||
.. option:: --flatten_names
|
||||
|
||||
Use flatten names (no wildcards) in SDC files
|
||||
|
||||
.. option:: --time_unit <string>
|
||||
|
||||
Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
|
||||
|
||||
|
||||
.. option:: --output_hierarchy
|
||||
|
||||
Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks.
|
||||
|
||||
.. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric``
|
||||
|
||||
.. option:: --constrain_global_port
|
||||
|
||||
Constrain all the global ports of FPGA fabric.
|
||||
|
||||
.. option:: --constrain_non_clock_global_port
|
||||
|
||||
Constrain all the non-clock global ports as clocks ports of FPGA fabric
|
||||
|
||||
.. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well.
|
||||
|
||||
.. option:: --constrain_grid
|
||||
|
||||
Constrain all the grids of FPGA fabric
|
||||
|
||||
.. option:: --constrain_sb
|
||||
|
||||
Constrain all the switch blocks of FPGA fabric
|
||||
|
||||
.. option:: --constrain_cb
|
||||
|
||||
Constrain all the connection blocks of FPGA fabric
|
||||
|
||||
.. option:: --constrain_configurable_memory_outputs
|
||||
|
||||
Constrain all the outputs of configurable memories of FPGA fabric
|
||||
|
||||
.. option:: --constrain_routing_multiplexer_outputs
|
||||
|
||||
Constrain all the outputs of routing multiplexer of FPGA fabric
|
||||
|
||||
.. option:: --constrain_switch_block_outputs
|
||||
|
||||
Constrain all the outputs of switch blocks of FPGA fabric
|
||||
|
||||
.. option:: --constrain_zero_delay_paths
|
||||
|
||||
Constrain all the zero-delay paths in FPGA fabric
|
||||
|
||||
.. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Enable verbose output
|
||||
|
||||
- ``--verbose`` Enable verbose output
|
||||
|
||||
write_configuration_chain_sdc
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Write the SDC file to constrain the timing for configuration chain. The timing constraints will always start from the first output (Q) of a Configuration Chain Flip-flop (CCFF) and ends at the inputs of the next CCFF in the chain. Note that Qb of CCFF will not be constrained!
|
||||
|
||||
- ``--file`` or ``-f`` Specify the output SDC file
|
||||
|
||||
- ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
|
||||
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
- ``--max_delay`` Specify the maximum delay to be used. The timing value should follow the time unit defined in this command.
|
||||
|
||||
- ``--min_delay`` Specify the minimum delay to be used. The timing value should follow the time unit defined in this command.
|
||||
|
||||
.. note::
|
||||
Only applicable when configuration chain is used as configuration protocol
|
||||
Specify the output SDC file. For example, ``--file cc_chain.sdc``
|
||||
|
||||
.. option:: --time_unit <string>
|
||||
|
||||
Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
|
||||
|
||||
.. option:: --max_delay <float>
|
||||
|
||||
Specify the maximum delay to be used. The timing value should follow the time unit defined in this command.
|
||||
|
||||
.. option:: --min_delay <float>
|
||||
|
||||
Specify the minimum delay to be used. The timing value should follow the time unit defined in this command.
|
||||
|
||||
.. note:: Only applicable when configuration chain is used as configuration protocol
|
||||
|
||||
write_sdc_disable_timing_configure_ports
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Write the SDC file to disable timing for configure ports of programmable modules. The SDC aims to break the combinational loops across FPGAs and avoid false path timing to be visible to timing analyzers
|
||||
|
||||
- ``--file`` or ``-f`` Specify the output SDC file
|
||||
|
||||
- ``--flatten_names`` Use flatten names (no wildcards) in SDC files
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
Specify the output SDC file. For example, ``--file disable_config_timing.sdc``.
|
||||
|
||||
.. option:: --flatten_names
|
||||
|
||||
Use flatten names (no wildcards) in SDC files
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
write_analysis_sdc
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
|
||||
- ``--file`` or ``-f`` Specify the output directory for SDC files
|
||||
|
||||
- ``--flatten_names`` Use flatten names (no wildcards) in SDC files
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
- ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
|
||||
Specify the output directory for SDC files. For example, ``--file counter_sta_analysis.sdc``
|
||||
|
||||
.. option:: --flatten_names
|
||||
|
||||
Use flatten names (no wildcards) in SDC files
|
||||
|
||||
.. option:: --time_unit <string>
|
||||
|
||||
Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
|
||||
|
|
|
|||
|
|
@ -8,43 +8,78 @@ write_fabric_verilog
|
|||
|
||||
Write the Verilog netlist for FPGA fabric based on module graph
|
||||
|
||||
- ``--file`` or ``-f`` Specify the output directory for the Verilog netlists
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
- ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
|
||||
Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/``
|
||||
|
||||
- ``--include_timing`` Output timing information to Verilog netlists for primitive modules
|
||||
.. option:: --explicit_port_mapping
|
||||
|
||||
Use explicit port mapping when writing the Verilog netlists
|
||||
|
||||
.. option:: --include_timing
|
||||
|
||||
Output timing information to Verilog netlists for primitive modules
|
||||
|
||||
- ``--include_signal_init`` Output signal initialization to Verilog netlists for primitive modules
|
||||
.. option:: --include_signal_init
|
||||
|
||||
- ``--support_icarus_simulator`` Output Verilog netlists with syntax that iVerilog simulatorcan accept
|
||||
Output signal initialization to Verilog netlists for primitive modules
|
||||
|
||||
- ``--print_user_defined_template`` Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
|
||||
.. option:: --support_icarus_simulator
|
||||
|
||||
Output Verilog netlists with syntax that iVerilog simulatorcan accept
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --print_user_defined_template
|
||||
|
||||
Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
write_verilog_testbench
|
||||
~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Write the Verilog testbench for FPGA fabric
|
||||
|
||||
- ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench``
|
||||
|
||||
- ``--fabric_netlist_file_path`` Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names.
|
||||
.. option:: --fabric_netlist_file_path <string>
|
||||
|
||||
- ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
|
||||
Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v``
|
||||
|
||||
- ``--pin_constraints_file`` specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`.
|
||||
.. option:: --reference_benchmark_file_path <string>
|
||||
|
||||
- ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
|
||||
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
|
||||
|
||||
.. option:: --pin_constraints_file <string> or -pcf <string>
|
||||
|
||||
Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml``
|
||||
Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`.
|
||||
|
||||
.. option:: --fast_configuration
|
||||
|
||||
Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
|
||||
|
||||
.. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.
|
||||
|
||||
- ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
.. option:: --print_top_testbench
|
||||
|
||||
- ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification
|
||||
Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
|
||||
- ``--print_preconfig_top_testbench`` Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
.. option:: --print_formal_verification_top_netlist
|
||||
|
||||
- ``--print_simulation_ini`` Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
Generate a top-level module which can be used in formal verification
|
||||
|
||||
- ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
|
||||
.. option:: --print_preconfig_top_testbench
|
||||
|
||||
Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
|
||||
.. option:: --print_simulation_ini <string>
|
||||
|
||||
Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts. For example, ``--print_simulation_ini /temp/testbench/sim.ini``
|
||||
|
||||
.. option:: --explicit_port_mapping
|
||||
|
||||
Use explicit port mapping when writing the Verilog netlists
|
||||
|
|
|
|||
|
|
@ -8,56 +8,85 @@ read_openfpga_arch
|
|||
|
||||
Read the XML file about architecture description (see details in :ref:`arch_generality`)
|
||||
|
||||
- ``--file`` or ``-f`` Specify the file name
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
Specify the file name. For example, ``--file openfpga_arch.xml``
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
write_openfpga_arch
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Write the OpenFPGA XML architecture file to a file
|
||||
|
||||
- ``--file`` or ``-f`` Specify the file name
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
Specify the file name. For example, ``--file arch_echo.xml``
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
read_openfpga_simulation_setting
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Read the XML file about simulation settings (see details in :ref:`simulation_setting`)
|
||||
|
||||
- ``--file`` or ``-f`` Specify the file name
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
Specify the file name. For example, ``--file auto_simulation_setting.xml``
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
write_openfpga_simulation_setting
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Write the OpenFPGA XML simulation settings to a file
|
||||
|
||||
- ``--file`` or ``-f`` Specify the file name
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
Specify the file name. For example, ``--file auto_simulation_setting_echo.xml``.
|
||||
See details about file format at :ref:`simulation_setting`.
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
link_openfpga_arch
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Annotate the OpenFPGA architecture to VPR data base
|
||||
|
||||
- ``--activity_file`` Specify the signal activity file
|
||||
.. option:: --activity_file <string>
|
||||
|
||||
- ``--sort_gsb_chan_node_in_edges`` Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
|
||||
Specify the signal activity file. For example, ``--activity_file counter.act``.
|
||||
This is required when users wants OpenFPGA to automatically find the number of clocks in simulations. See details at :ref:`simulation_setting`.
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --sort_gsb_chan_node_in_edges
|
||||
|
||||
Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
write_gsb_to_xml
|
||||
~~~~~~~~~~~~~~~~
|
||||
|
||||
Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
|
||||
|
||||
- ``--file`` or ``-f`` Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
|
||||
For example, ``--file /temp/gsb_output``
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
.. note:: This command is used to help users to study the difference between GSBs
|
||||
|
||||
|
|
@ -69,9 +98,13 @@ check_netlist_naming_conflict
|
|||
|
||||
.. warning:: This command may be deprecated in future when it is merged to VPR upstream
|
||||
|
||||
- ``--fix`` Apply fix-up to the names that violate the syntax
|
||||
.. option:: --fix
|
||||
|
||||
- ``--report <.xml>`` Report the naming fix-up to a log file
|
||||
Apply fix-up to the names that violate the syntax
|
||||
|
||||
.. option:: --report <string>
|
||||
|
||||
Report the naming fix-up to an XML-based log file. For example, ``--report rename.xml``
|
||||
|
||||
pb_pin_fixup
|
||||
~~~~~~~~~~~~
|
||||
|
|
@ -81,7 +114,9 @@ pb_pin_fixup
|
|||
|
||||
.. warning:: This command may be deprecated in future when it is merged to VPR upstream
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
lut_truth_table_fixup
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
|
@ -90,7 +125,9 @@ lut_truth_table_fixup
|
|||
|
||||
.. warning:: This command may be deprecated in future when it is merged to VPR upstream
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
.. _cmd_build_fabric:
|
||||
|
||||
|
|
@ -99,21 +136,35 @@ build_fabric
|
|||
|
||||
Build the module graph.
|
||||
|
||||
- ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
|
||||
.. option:: --compress_routing
|
||||
|
||||
Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
|
||||
|
||||
- ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
|
||||
.. option:: --duplicate_grid_pin
|
||||
|
||||
- ``--load_fabric_key <xml_file>`` Load an external fabric key from an XML file.
|
||||
Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
|
||||
|
||||
- ``--generate_fabric_key`` Generate a fabric key in a random way
|
||||
.. option:: --load_fabric_key <string>
|
||||
|
||||
- ``--write_fabric_key <xml_file>`` Output current fabric key to an XML file
|
||||
Load an external fabric key from an XML file. For example, ``--load_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
|
||||
|
||||
- ``--frame_view`` Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
|
||||
.. option:: --generate_random_fabric_key
|
||||
|
||||
Generate a fabric key in a random way
|
||||
|
||||
.. option:: --write_fabric_key <string>.
|
||||
|
||||
Output current fabric key to an XML file. For example, ``--write_fabric_key fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
|
||||
|
||||
.. option:: --frame_view
|
||||
|
||||
Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
|
||||
|
||||
.. warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
|
||||
|
||||
|
|
@ -122,10 +173,16 @@ write_fabric_hierarchy
|
|||
|
||||
Write the hierarchy of FPGA fabric graph to a plain-text file
|
||||
|
||||
- ``--file`` or ``-f`` Specify the file name to write the hierarchy.
|
||||
.. option:: --file <string> or -f <string>
|
||||
|
||||
Specify the file name to write the hierarchy.
|
||||
|
||||
- ``--depth`` Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
|
||||
.. option:: --depth <int>
|
||||
|
||||
- ``--verbose`` Show verbose log
|
||||
Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
|
||||
|
||||
.. option:: --verbose
|
||||
|
||||
Show verbose log
|
||||
|
||||
.. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).
|
||||
|
|
|
|||
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@ -17,15 +17,15 @@ OpenFPGA also provides native bitstream generation support based the same XML-ba
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OpenFPGA can support any architecture that VPR can describe, covering most of the architecture enhancements available in modern FPGAs, and hence unlocks a large design space in prototyping customizable FPGAs. In addition, OpenFPGA provides enriched syntax which allows users to customized primitive circuit designed downto transistor-level parameters. This helps developers to customize the P.P.A. (Power, Performance and Area) to the best. All these features open the door of prototyping/studying flexible FPGAs to a small group of junior engineers or researchers.
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In terms of tool functionality, OpenFPGA consists of the following parts: FPGA-Verilog, FPGA-SDC, FPGA-Bitstream and FPGA-SPICE.
|
||||
The rest of this section will focus on detailed motivation on each of them, as depicted in :numref:`fig_openfpga_flow`.
|
||||
The rest of this section will focus on detailed motivation on each of them, as depicted in :numref:`fig_openfpga_framework`.
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||||
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||||
.. _fig_openfpga_flow:
|
||||
.. _fig_openfpga_framework:
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||||
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.. figure:: ./figures/openfpga_flow.png
|
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.. figure:: ./figures/openfpga_framework.svg
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:scale: 50%
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:alt: Design flows avaiable in OpenFPGA
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:alt: OpenFPGA framework
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Design flows in different purposes using OpenFPGA
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OpenFPGA: a unified framework for chip designer and FPGA programmer
|
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||||
Fully Customizable Architecture
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||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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|
|
@ -59,7 +59,7 @@ FPGA-Verilog is designed to output flexible and standard Verilog netlists, enabl
|
|||
|
||||
.. _fig_fpga_verilog_motivation:
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||||
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.. figure:: ./figures/fpga_verilog_motivation.png
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.. figure:: ./figures/fpga_verilog_motivation.svg
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:scale: 25%
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:alt: Flexible netlist format support by FPGA-Verilog to enable various backend choices
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@ -73,6 +73,7 @@ FPGA-SDC
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Design constraints are indepensible in modern ASIC design flows to guarantee the performance level.
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OpenFPGA includes a rich SDC generator in the OpenFPGA framework to deal with both PnR constraints and sign-off timing analysis.
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Our flow automatically generates two sets of SDC files.
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- The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable wellcontrolled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. OpenFPGA allows users to define timing constraints in the architecture description and outputs timing constraints in standard format, enabling fully timing constrained backend flow (see :ref:`fig_fpga_sdc_motivation`).
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- The second set of SDC is designed for the timing analysis of a benchmark at the post P&R stage.
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|
||||
<text transform="translate(428.97687 837.6917)" fill="black">
|
||||
<tspan font-family="Times New Roman" font-size="16" font-weight="400" fill="black" x="14.887966" y="14">GDSII</tspan>
|
||||
</text>
|
||||
</g>
|
||||
<g id="Line_35883">
|
||||
<line x1="465.19687" y1="866.2625" x2="465.19687" y2="875.9533" marker-end="url(#FilledArrow_Marker)" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
|
||||
</g>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
After Width: | Height: | Size: 46 KiB |
|
|
@ -10,7 +10,7 @@ To enable various design purposes, OpenFPGA integrates several tools to i.e., FP
|
|||
|
||||
.. _fig_openfpga_tools:
|
||||
|
||||
.. figure:: figures/openfpga_tools.png
|
||||
.. figure:: figures/openfpga_tools.svg
|
||||
:scale: 25%
|
||||
:alt: map to buried treasure
|
||||
|
||||
|
|
|
|||
|
|
@ -143,11 +143,17 @@ class Shell {
|
|||
/* Start the interactive mode, where users will type-in command by command */
|
||||
void run_interactive_mode(T& context, const bool& quiet_mode = false);
|
||||
/* Start the script mode, where users provide a file which includes all the commands to run */
|
||||
void run_script_mode(const char* script_file_name, T& context);
|
||||
void run_script_mode(const char* script_file_name,
|
||||
T& context,
|
||||
const bool& batch_mode = false);
|
||||
/* Print all the commands by their classes. This is actually the help desk */
|
||||
void print_commands() const;
|
||||
/* Find the exit code (assume quit shell now) */
|
||||
int exit_code() const;
|
||||
/* Show statistics of errors during command execution */
|
||||
int execution_errors() const;
|
||||
/* Quit the shell */
|
||||
void exit() const;
|
||||
void exit(const int& init_err = 0) const;
|
||||
private: /* Private executors */
|
||||
/* Execute a command, the command line is the user's input to launch a command
|
||||
* The common_context is the data structure to exchange data between commands
|
||||
|
|
|
|||
|
|
@ -272,7 +272,9 @@ void Shell<T>::run_interactive_mode(T& context, const bool& quiet_mode) {
|
|||
}
|
||||
|
||||
template <class T>
|
||||
void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
|
||||
void Shell<T>::run_script_mode(const char* script_file_name,
|
||||
T& context,
|
||||
const bool& batch_mode) {
|
||||
|
||||
time_start_ = std::clock();
|
||||
|
||||
|
|
@ -356,17 +358,28 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
|
|||
/* Empty the line ready to start a new line */
|
||||
cmd_line.clear();
|
||||
|
||||
/* Check the execution status of the command, if fatal error happened, we should abort immediately */
|
||||
/* Check the execution status of the command,
|
||||
* if fatal error happened, we should abort immediately
|
||||
*/
|
||||
if (CMD_EXEC_FATAL_ERROR == status) {
|
||||
VTR_LOG("Fatal error occurred!\nAbort and enter interactive mode\n");
|
||||
VTR_LOG("Fatal error occurred!\n");
|
||||
/* If in the batch mode, we will exit with errors */
|
||||
VTR_LOGV(batch_mode, "OpenFPGA Abort\n");
|
||||
if (batch_mode) {
|
||||
exit(CMD_EXEC_FATAL_ERROR);
|
||||
}
|
||||
/* If not in the batch mode, we will got to interactive mode */
|
||||
VTR_LOGV(!batch_mode, "Enter interactive mode\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
fp.close();
|
||||
|
||||
/* Return to interactive mode, stay tuned */
|
||||
run_interactive_mode(context, true);
|
||||
/* If not in batch mode, switch to interactive mode, stay tuned */
|
||||
if (!batch_mode) {
|
||||
run_interactive_mode(context, true);
|
||||
}
|
||||
}
|
||||
|
||||
template <class T>
|
||||
|
|
@ -392,7 +405,7 @@ void Shell<T>::print_commands() const {
|
|||
}
|
||||
|
||||
template <class T>
|
||||
void Shell<T>::exit() const {
|
||||
int Shell<T>::exit_code() const {
|
||||
/* Check all the command status, if we see fatal errors or minor errors, we drop an error code */
|
||||
int exit_code = 0;
|
||||
for (const int& status : command_status_) {
|
||||
|
|
@ -403,23 +416,41 @@ void Shell<T>::exit() const {
|
|||
}
|
||||
}
|
||||
|
||||
return exit_code;
|
||||
}
|
||||
|
||||
template <class T>
|
||||
int Shell<T>::execution_errors() const {
|
||||
/* Show error message if we detect any errors */
|
||||
int num_err = 0;
|
||||
if (0 != exit_code) {
|
||||
VTR_LOG("\n");
|
||||
for (const ShellCommandId& cmd : commands()) {
|
||||
if (command_status_[cmd] == CMD_EXEC_FATAL_ERROR) {
|
||||
VTR_LOG_ERROR("Command '%s' execution has fatal errors\n",
|
||||
commands_[cmd].name().c_str());
|
||||
num_err++;
|
||||
}
|
||||
|
||||
if (command_status_[cmd] == CMD_EXEC_MINOR_ERROR) {
|
||||
VTR_LOG_ERROR("Command '%s' execution has minor errors\n",
|
||||
commands_[cmd].name().c_str());
|
||||
num_err++;
|
||||
}
|
||||
|
||||
for (const ShellCommandId& cmd : commands()) {
|
||||
if (command_status_[cmd] == CMD_EXEC_FATAL_ERROR) {
|
||||
VTR_LOG_ERROR("Command '%s' execution has fatal errors\n",
|
||||
commands_[cmd].name().c_str());
|
||||
num_err++;
|
||||
}
|
||||
|
||||
if (command_status_[cmd] == CMD_EXEC_MINOR_ERROR) {
|
||||
VTR_LOG_ERROR("Command '%s' execution has minor errors\n",
|
||||
commands_[cmd].name().c_str());
|
||||
num_err++;
|
||||
}
|
||||
}
|
||||
|
||||
return num_err;
|
||||
}
|
||||
|
||||
template <class T>
|
||||
void Shell<T>::exit(const int& init_err) const {
|
||||
/* Check all the command status, if we see fatal errors or minor errors, we drop an error code */
|
||||
int shell_exit_code = exit_code() | init_err;
|
||||
|
||||
/* Show error message if we detect any errors */
|
||||
int num_err = init_err;
|
||||
if (CMD_EXEC_SUCCESS != shell_exit_code) {
|
||||
VTR_LOG("\n");
|
||||
num_err += execution_errors();
|
||||
}
|
||||
|
||||
VTR_LOG("\nFinish execution with %d errors\n",
|
||||
|
|
@ -431,7 +462,7 @@ void Shell<T>::exit() const {
|
|||
VTR_LOG("\nThank you for using %s!\n",
|
||||
name().c_str());
|
||||
|
||||
std::exit(exit_code);
|
||||
std::exit(shell_exit_code);
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
|
|
@ -460,6 +491,7 @@ int Shell<T>::execute_command(const char* cmd_line,
|
|||
commands_[dep_cmd].name().c_str(), commands_[cmd_id].name().c_str());
|
||||
/* Echo the command help desk */
|
||||
print_command_options(commands_[cmd_id]);
|
||||
command_status_[cmd_id] = CMD_EXEC_FATAL_ERROR;
|
||||
return CMD_EXEC_FATAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
|
@ -494,6 +526,7 @@ int Shell<T>::execute_command(const char* cmd_line,
|
|||
if (false == parse_command(tokens, commands_[cmd_id], command_contexts_[cmd_id])) {
|
||||
/* Echo the command */
|
||||
print_command_options(commands_[cmd_id]);
|
||||
command_status_[cmd_id] = CMD_EXEC_FATAL_ERROR;
|
||||
return CMD_EXEC_FATAL_ERROR;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,11 +2,67 @@ cmake_minimum_required(VERSION 3.9)
|
|||
|
||||
project("libopenfpgautil")
|
||||
|
||||
#Version info
|
||||
set(OPENFPGA_VERSION_FILE_IN ${CMAKE_CURRENT_SOURCE_DIR}/src/openfpga_version.cpp.in)
|
||||
set(OPENFPGA_VERSION_FILE_OUT ${CMAKE_CURRENT_BINARY_DIR}/openfpga_version.cpp)
|
||||
|
||||
#Compiler info
|
||||
set(OPENFPGA_COMPILER_INFO "${CMAKE_CXX_COMPILER_ID} ${CMAKE_CXX_COMPILER_VERSION} on ${CMAKE_SYSTEM} ${CMAKE_SYSTEM_PROCESSOR}")
|
||||
|
||||
set(OPENFPGA_BUILD_INFO "${CMAKE_BUILD_TYPE}")
|
||||
|
||||
#Set default version numbers in case not specified
|
||||
if(NOT DEFINED OPENFPGA_VERSION_MAJOR)
|
||||
set(OPENFPGA_VERSION_MAJOR 0)
|
||||
endif()
|
||||
|
||||
if(NOT DEFINED OPENFPGA_VERSION_MINOR)
|
||||
set(OPENFPGA_VERSION_MINOR 0)
|
||||
endif()
|
||||
|
||||
if(NOT DEFINED OPENFPGA_VERSION_PATCH)
|
||||
set(OPENFPGA_VERSION_PATCH 0)
|
||||
endif()
|
||||
|
||||
set(OPENFPGA_BUILD_INFO "${OPENFPGA_BUILD_INFO} ASSERT_LEVEL=${VTR_ASSERT_LEVEL}")
|
||||
|
||||
# We always update the openfpga_version.cpp file every time the project is built,
|
||||
# to ensure the git revision and dirty status are up to date.
|
||||
#
|
||||
# We need to do this in two stages:
|
||||
#
|
||||
# 1) We build a custom target 'version' (which is always out of date) so it will always be run.
|
||||
# It touches the unprocessed version input file so it too will always be out of date.
|
||||
#
|
||||
# 2) The custom command depends on the touched version input file and generates the processed
|
||||
# version file, with updated values. The custom command uses the configure_version.cmake
|
||||
# script to generate the up-to-date openfpga_version.cpp
|
||||
add_custom_target(openfpga_version ALL
|
||||
COMMAND ${CMAKE_COMMAND} -E touch ${OPENFPGA_VERSION_FILE_IN})
|
||||
|
||||
add_custom_command(OUTPUT ${OPENFPGA_VERSION_FILE_OUT}
|
||||
COMMAND ${CMAKE_COMMAND}
|
||||
-D IN_FILE=${OPENFPGA_VERSION_FILE_IN}
|
||||
-D OUT_FILE=${OPENFPGA_VERSION_FILE_OUT}
|
||||
-D OPENFPGA_VERSION_MAJOR=${OPENFPGA_VERSION_MAJOR}
|
||||
-D OPENFPGA_VERSION_MINOR=${OPENFPGA_VERSION_MINOR}
|
||||
-D OPENFPGA_VERSION_PATCH=${OPENFPGA_VERSION_PATCH}
|
||||
-D OPENFPGA_VERSION_PRERELEASE=${OPENFPGA_VERSION_PRERELEASE}
|
||||
-D OPENFPGA_COMPILER_INFO=${OPENFPGA_COMPILER_INFO}
|
||||
-D OPENFPGA_BUILD_INFO=${OPENFPGA_BUILD_INFO}
|
||||
-P ${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules/configure_version.cmake
|
||||
MAIN_DEPENDENCY ${OPENFPGA_VERSION_FILE_IN}
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
VERBATIM)
|
||||
|
||||
#file(GLOB_RECURSE EXEC_SOURCES test/main.cpp)
|
||||
file(GLOB_RECURSE LIB_SOURCES src/*.cpp)
|
||||
file(GLOB_RECURSE LIB_HEADERS src/*.h)
|
||||
files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
|
||||
|
||||
#Add the version file to the sources
|
||||
list(APPEND LIB_SOURCES ${OPENFPGA_VERSION_FILE_OUT})
|
||||
|
||||
#Remove test executable from library
|
||||
#list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCES})
|
||||
|
||||
|
|
@ -17,6 +73,9 @@ add_library(libopenfpgautil STATIC
|
|||
target_include_directories(libopenfpgautil PUBLIC ${LIB_INCLUDE_DIRS})
|
||||
set_target_properties(libopenfpgautil PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
|
||||
|
||||
#Ensure version is always up to date by requiring version to be run first
|
||||
add_dependencies(libopenfpgautil openfpga_version)
|
||||
|
||||
#Specify link-time dependancies
|
||||
target_link_libraries(libopenfpgautil
|
||||
libarchfpga
|
||||
|
|
|
|||
|
|
@ -0,0 +1,55 @@
|
|||
#
|
||||
# Versioning information
|
||||
#
|
||||
#Figure out the git revision
|
||||
find_package(Git QUIET)
|
||||
if(GIT_FOUND)
|
||||
exec_program(${GIT_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
ARGS describe --always --long --dirty
|
||||
OUTPUT_VARIABLE OPENFPGA_VCS_REVISION
|
||||
RETURN_VALUE GIT_DESCRIBE_RETURN_VALUE)
|
||||
|
||||
if(NOT GIT_DESCRIBE_RETURN_VALUE EQUAL 0)
|
||||
#Git describe failed, usually this means we
|
||||
#aren't in a git repo -- so don't set a VCS
|
||||
#revision
|
||||
set(OPENFPGA_VCS_REVISION "unkown")
|
||||
endif()
|
||||
|
||||
#Call again with exclude to get the revision excluding any tags
|
||||
#(i.e. just the commit ID and dirty flag)
|
||||
exec_program(${GIT_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
ARGS describe --always --long --dirty --exclude '*'
|
||||
OUTPUT_VARIABLE OPENFPGA_VCS_REVISION_SHORT
|
||||
RETURN_VALUE GIT_DESCRIBE_RETURN_VALUE)
|
||||
if(NOT GIT_DESCRIBE_RETURN_VALUE EQUAL 0)
|
||||
#Git describe failed, usually this means we
|
||||
#aren't in a git repo -- so don't set a VCS
|
||||
#revision
|
||||
set(OPENFPGA_VCS_REVISION_SHORT "unkown")
|
||||
endif()
|
||||
else()
|
||||
#Couldn't find git, so can't look-up VCS revision
|
||||
set(OPENFPGA_VCS_REVISION "unkown")
|
||||
set(OPENFPGA_VCS_REVISION_SHORT "unkown")
|
||||
endif()
|
||||
|
||||
|
||||
#Set the version according to semver.org
|
||||
set(OPENFPGA_VERSION "${OPENFPGA_VERSION_MAJOR}.${OPENFPGA_VERSION_MINOR}.${OPENFPGA_VERSION_PATCH}")
|
||||
if(OPENFPGA_VERSION_PRERELEASE)
|
||||
set(OPENFPGA_VERSION "${OPENFPGA_VERSION}-${OPENFPGA_VERSION_PRERELEASE}")
|
||||
endif()
|
||||
set(OPENFPGA_VERSION_SHORT ${OPENFPGA_VERSION})
|
||||
if(OPENFPGA_VCS_REVISION)
|
||||
set(OPENFPGA_VERSION "${OPENFPGA_VERSION}+${OPENFPGA_VCS_REVISION_SHORT}")
|
||||
endif()
|
||||
|
||||
#Other build meta-data
|
||||
string(TIMESTAMP OPENFPGA_BUILD_TIMESTAMP)
|
||||
set(OPENFPGA_BUILD_TIMESTAMP "${OPENFPGA_BUILD_TIMESTAMP}")
|
||||
set(OPENFPGA_BUILD_INFO "${OPENFPGA_BUILD_INFO}")
|
||||
|
||||
message(STATUS "OpenFPGA Version: ${OPENFPGA_VERSION}")
|
||||
|
||||
configure_file(${IN_FILE} ${OUT_FILE})
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
#include "openfpga_version.h"
|
||||
|
||||
//This file is automatically processed by CMAKE and replaces
|
||||
//the values between ampersand's with the releveant CMAKE variable
|
||||
//before being compiled.
|
||||
namespace openfpga {
|
||||
const char* VERSION = "@OPENFPGA_VERSION@";
|
||||
const char* VERSION_SHORT = "@OPENFPGA_VERSION_SHORT@";
|
||||
|
||||
const size_t VERSION_MAJOR = @OPENFPGA_VERSION_MAJOR@;
|
||||
const size_t VERSION_MINOR = @OPENFPGA_VERSION_MINOR@;
|
||||
const size_t VERSION_PATCH = @OPENFPGA_VERSION_PATCH@;
|
||||
const char* VERSION_PRERELEASE = "@OPENFPGA_VERSION_PRERELEASE@";
|
||||
|
||||
const char* VCS_REVISION = "@OPENFPGA_VCS_REVISION@";
|
||||
const char* VCS_REVISION_SHORT = "@OPENFPGA_VCS_REVISION_SHORT@";
|
||||
|
||||
const char* COMPILER = "@OPENFPGA_COMPILER_INFO@";
|
||||
const char* BUILD_TIMESTAMP = "@OPENFPGA_BUILD_TIMESTAMP@";
|
||||
const char* BUILD_INFO = "@OPENFPGA_BUILD_INFO@";
|
||||
}
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#ifndef OPENFPGA_VERSION_H
|
||||
#define OPENFPGA_VERSION_H
|
||||
#include <cstddef>
|
||||
|
||||
namespace openfpga {
|
||||
extern const char* VERSION;
|
||||
extern const char* VERSION_SHORT;
|
||||
|
||||
extern const size_t VERSION_MAJOR;
|
||||
extern const size_t VERSION_MINOR;
|
||||
extern const size_t VERSION_PATCH;
|
||||
extern const char* VERSION_PRERELEASE;
|
||||
|
||||
extern const char* VCS_REVISION;
|
||||
extern const char* COMPILER;
|
||||
extern const char* BUILD_TIMESTAMP;
|
||||
extern const char* BUILD_INFO;
|
||||
} // namespace openfpga
|
||||
|
||||
#endif
|
||||
|
|
@ -237,6 +237,12 @@ int annotate_simulation_setting(const AtomContext& atom_ctx,
|
|||
*/
|
||||
VTR_LOG("User specified the number of operating clock cycles to be inferred from signal activities\n");
|
||||
|
||||
/* Error out if net activity is not defined */
|
||||
if (true == net_activity.empty()) {
|
||||
VTR_LOG_ERROR("Signal activities are not defined!\nPlease check if activity file is given and properly generated!\n");
|
||||
return CMD_EXEC_FATAL_ERROR;
|
||||
}
|
||||
|
||||
/* Use a fixed simulation window size now. TODO: this could be specified by users */
|
||||
size_t num_clock_cycles = recommend_num_sim_clock_cycle(atom_ctx,
|
||||
net_activity,
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
/********************************************************************
|
||||
* Add basic commands to the OpenFPGA shell interface, including:
|
||||
* - exit
|
||||
* - version
|
||||
* - help
|
||||
*******************************************************************/
|
||||
#include "openfpga_title.h"
|
||||
#include "basic_command.h"
|
||||
|
||||
/* begin namespace openfpga */
|
||||
|
|
@ -17,7 +19,15 @@ void add_basic_commands(openfpga::Shell<OpenfpgaContext>& shell) {
|
|||
shell.set_command_class(shell_cmd_exit_id, basic_cmd_class);
|
||||
shell.set_command_execute_function(shell_cmd_exit_id, [shell](){shell.exit();});
|
||||
|
||||
/* Note: help must be the last to add because the linking to execute function will do a snapshot on the shell */
|
||||
/* Version */
|
||||
Command shell_cmd_version("version");
|
||||
ShellCommandId shell_cmd_version_id = shell.add_command(shell_cmd_version, "Show version information");
|
||||
shell.set_command_class(shell_cmd_version_id, basic_cmd_class);
|
||||
shell.set_command_execute_function(shell_cmd_version_id, print_openfpga_version_info);
|
||||
|
||||
/* Note:
|
||||
* help MUST be the last to add because the linking to execute function will do a snapshot on the shell
|
||||
*/
|
||||
Command shell_cmd_help("help");
|
||||
ShellCommandId shell_cmd_help_id = shell.add_command(shell_cmd_help, "Launch help desk");
|
||||
shell.set_command_class(shell_cmd_help_id, basic_cmd_class);
|
||||
|
|
|
|||
|
|
@ -67,7 +67,6 @@ class OpenfpgaContext : public Context {
|
|||
const openfpga::FabricBitstream& fabric_bitstream() const { return fabric_bitstream_; }
|
||||
const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
|
||||
const openfpga::FabricGlobalPortInfo& fabric_global_port_info() const { return fabric_global_port_info_; }
|
||||
const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
|
||||
const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
|
||||
const openfpga::NetlistManager& spice_netlists() const { return spice_netlists_; }
|
||||
public: /* Public mutators */
|
||||
|
|
@ -88,7 +87,6 @@ class OpenfpgaContext : public Context {
|
|||
openfpga::FabricBitstream& mutable_fabric_bitstream() { return fabric_bitstream_; }
|
||||
openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
|
||||
openfpga::FabricGlobalPortInfo& mutable_fabric_global_port_info() { return fabric_global_port_info_; }
|
||||
std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
|
||||
openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
|
||||
openfpga::NetlistManager& mutable_spice_netlists() { return spice_netlists_; }
|
||||
private: /* Internal data */
|
||||
|
|
@ -138,9 +136,6 @@ class OpenfpgaContext : public Context {
|
|||
openfpga::NetlistManager verilog_netlists_;
|
||||
openfpga::NetlistManager spice_netlists_;
|
||||
|
||||
/* Net activities of users' implementation */
|
||||
std::unordered_map<AtomNetId, t_net_power> net_activity_;
|
||||
|
||||
/* Flow status */
|
||||
openfpga::FlowManager flow_manager_;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
|
|||
|
||||
vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
|
||||
|
||||
// CommandOptionId opt_activity_file = cmd.option("activity_file");
|
||||
CommandOptionId opt_activity_file = cmd.option("activity_file");
|
||||
CommandOptionId opt_sort_edge = cmd.option("sort_gsb_chan_node_in_edges");
|
||||
CommandOptionId opt_verbose = cmd.option("verbose");
|
||||
|
||||
|
|
@ -148,8 +148,11 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
|
|||
* should be inferred from FPGA implmentation
|
||||
* - When FPGA-SPICE is enabled
|
||||
*/
|
||||
// openfpga_ctx.mutable_net_activity() = read_activity(g_vpr_ctx.atom().nlist,
|
||||
//cmd_context.option_value(cmd, opt_activity_file).c_str());
|
||||
std::unordered_map<AtomNetId, t_net_power> net_activity;
|
||||
if (true == cmd_context.option_enable(cmd, opt_activity_file)) {
|
||||
net_activity = read_activity(g_vpr_ctx.atom().nlist,
|
||||
cmd_context.option_value(cmd, opt_activity_file).c_str());
|
||||
}
|
||||
|
||||
/* TODO: Annotate the number of clock cycles and clock frequency by following VPR results
|
||||
* We SHOULD create a new simulation setting for OpenFPGA use only
|
||||
|
|
@ -159,11 +162,11 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
|
|||
* TODO: This will be removed when openfpga flow is updated
|
||||
*/
|
||||
//openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
|
||||
//if (CMD_EXEC_FATAL_ERROR == annotate_simulation_setting(g_vpr_ctx.atom(),
|
||||
// openfpga_ctx.net_activity(),
|
||||
// openfpga_ctx.mutable_simulation_setting())) {
|
||||
//return CMD_EXEC_FATAL_ERROR;
|
||||
//}
|
||||
if (CMD_EXEC_FATAL_ERROR == annotate_simulation_setting(g_vpr_ctx.atom(),
|
||||
net_activity,
|
||||
openfpga_ctx.mutable_simulation_setting())) {
|
||||
return CMD_EXEC_FATAL_ERROR;
|
||||
}
|
||||
|
||||
/* TODO: should identify the error code from internal function execution */
|
||||
return CMD_EXEC_SUCCESS;
|
||||
|
|
|
|||
|
|
@ -125,8 +125,8 @@ ShellCommandId add_openfpga_link_arch_command(openfpga::Shell<OpenfpgaContext>&
|
|||
Command shell_cmd("link_openfpga_arch");
|
||||
|
||||
/* Add an option '--activity_file'*/
|
||||
//CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", true, "file path to the signal activity");
|
||||
//shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING);
|
||||
CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", false, "file path to the signal activity");
|
||||
shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING);
|
||||
|
||||
/* Add an option '--sort_gsb_chan_node_in_edges'*/
|
||||
shell_cmd.add_option("sort_gsb_chan_node_in_edges", false, "Sort all the incoming edges for each routing track output node in General Switch Blocks (GSBs)");
|
||||
|
|
|
|||
|
|
@ -2,7 +2,10 @@
|
|||
* This file includes the functions to create the title page
|
||||
* which introduces generality of OpenFPGA framework
|
||||
*******************************************************************/
|
||||
#include "vtr_log.h"
|
||||
|
||||
#include "openfpga_title.h"
|
||||
#include "openfpga_version.h"
|
||||
|
||||
/********************************************************************
|
||||
* Generate a string of openfpga title introduction
|
||||
|
|
@ -51,3 +54,17 @@ std::string create_openfpga_title() {
|
|||
|
||||
return title;
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* Generate a string of openfpga title introduction
|
||||
* This is mainly used when launching OpenFPGA shell
|
||||
*******************************************************************/
|
||||
void print_openfpga_version_info() {
|
||||
/* Display version */
|
||||
VTR_LOG("Version: %s\n", openfpga::VERSION);
|
||||
VTR_LOG("Revision: %s\n", openfpga::VCS_REVISION);
|
||||
VTR_LOG("Compiled: %s\n", openfpga::BUILD_TIMESTAMP);
|
||||
VTR_LOG("Compiler: %s\n", openfpga::COMPILER);
|
||||
VTR_LOG("Build Info: %s\n", openfpga::BUILD_INFO);
|
||||
VTR_LOG("\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,4 +11,6 @@
|
|||
*******************************************************************/
|
||||
std::string create_openfpga_title();
|
||||
|
||||
void print_openfpga_version_info();
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
|
|||
/* There should be only one operating clock!
|
||||
* TODO: this should be changed when developing multi-clock support!!!
|
||||
*/
|
||||
VTR_ASSERT(1 == operating_clock_ports.size());
|
||||
//VTR_ASSERT(1 == operating_clock_ports.size());
|
||||
|
||||
/* In this function, we support only 1 type of I/Os */
|
||||
std::vector<BasicPort> module_io_ports = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT);
|
||||
|
|
|
|||
|
|
@ -273,6 +273,11 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
|
|||
continue;
|
||||
}
|
||||
|
||||
/* Bypass unused output pads */
|
||||
if (ModuleManager::MODULE_GPOUT_PORT == module_manager.port_type(top_module, module_io_port_id)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Wire to a contant */
|
||||
BasicPort module_unused_io_port = module_manager.module_port(top_module, module_io_port_id);
|
||||
/* Set the port pin index */
|
||||
|
|
|
|||
|
|
@ -29,17 +29,27 @@ int main(int argc, char** argv) {
|
|||
|
||||
/* Create the command to launch shell in different modes */
|
||||
openfpga::Command start_cmd("OpenFPGA");
|
||||
/* Add two options:
|
||||
* '--interactive', -i': launch the interactive mode
|
||||
* '--file', -f': launch the script mode
|
||||
*/
|
||||
/* Add options to openfpga shell interface */
|
||||
/* '--interactive', -i': launch the interactive mode */
|
||||
openfpga::CommandOptionId opt_interactive = start_cmd.add_option("interactive", false, "Launch OpenFPGA in interactive mode");
|
||||
start_cmd.set_option_short_name(opt_interactive, "i");
|
||||
|
||||
/* '--file', -f': launch the script mode */
|
||||
openfpga::CommandOptionId opt_script_mode = start_cmd.add_option("file", false, "Launch OpenFPGA in script mode");
|
||||
start_cmd.set_option_require_value(opt_script_mode, openfpga::OPT_STRING);
|
||||
start_cmd.set_option_short_name(opt_script_mode, "f");
|
||||
|
||||
/* '--batch_execution': execute the script in batch mode.
|
||||
* Will exit immediately when fatal errors occurred
|
||||
*/
|
||||
openfpga::CommandOptionId opt_batch_exec = start_cmd.add_option("batch_execution", false, "Launch OpenFPGA in batch mode when running scripts");
|
||||
start_cmd.set_option_short_name(opt_batch_exec, "batch");
|
||||
|
||||
/* '--version', -v': print version information */
|
||||
openfpga::CommandOptionId opt_version = start_cmd.add_option("version", false, "Show OpenFPGA version");
|
||||
start_cmd.set_option_short_name(opt_version, "v");
|
||||
|
||||
/* '--help', -h': print help desk */
|
||||
openfpga::CommandOptionId opt_help = start_cmd.add_option("help", false, "Help desk");
|
||||
start_cmd.set_option_short_name(opt_help, "h");
|
||||
|
||||
|
|
@ -91,21 +101,31 @@ int main(int argc, char** argv) {
|
|||
/* Parse fail: Echo the command */
|
||||
openfpga::print_command_options(start_cmd);
|
||||
} else {
|
||||
/* Parse succeed. Start a shell */
|
||||
/* Parse succeed. Branch on options */
|
||||
/* Show version */
|
||||
if (true == start_cmd_context.option_enable(start_cmd, opt_version)) {
|
||||
print_openfpga_version_info();
|
||||
return 0;
|
||||
}
|
||||
/* Start a shell */
|
||||
if (true == start_cmd_context.option_enable(start_cmd, opt_interactive)) {
|
||||
|
||||
shell.run_interactive_mode(openfpga_context);
|
||||
return 0;
|
||||
return shell.exit_code();
|
||||
}
|
||||
|
||||
if (true == start_cmd_context.option_enable(start_cmd, opt_script_mode)) {
|
||||
shell.run_script_mode(start_cmd_context.option_value(start_cmd, opt_script_mode).c_str(),
|
||||
openfpga_context);
|
||||
return 0;
|
||||
openfpga_context,
|
||||
start_cmd_context.option_enable(start_cmd, opt_batch_exec));
|
||||
return shell.exit_code();
|
||||
}
|
||||
/* Reach here there is something wrong, show the help desk */
|
||||
openfpga::print_command_options(start_cmd);
|
||||
}
|
||||
|
||||
return 0;
|
||||
/* Reach here, it means shell execution has critical errors.
|
||||
* Return a code with fatal errors
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
clk 0.5 0.5
|
||||
addr_0 0.5 0.2
|
||||
addr_1 0.5 0.2
|
||||
d_in 0.5 0.2
|
||||
wr_en 0.5 0.2
|
||||
int 0.5 0.2
|
||||
d_out 0.25 0.25
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
.model asyn_spram_4x1
|
||||
.inputs clk addr_0 addr_1 d_in wr_en
|
||||
.outputs d_out
|
||||
|
||||
.subckt spram_4x1 clk=clk addr[0]=addr_0 addr[1]=addr_1 d_in=d_in wr_en=wr_en d_out=int
|
||||
|
||||
.names int d_out
|
||||
1 1
|
||||
|
||||
.end
|
||||
|
||||
.model spram_4x1
|
||||
.blackbox
|
||||
.inputs clk addr[0] addr[1] d_in wr_en
|
||||
.outputs d_out
|
||||
.end
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/////////////////////////////////////////
|
||||
// Functionality: 4x1 memory async read
|
||||
// Author: Aurelien Alacchi
|
||||
////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module asyn_spram_4x1(
|
||||
clk,
|
||||
addr_0,
|
||||
addr_1,
|
||||
d_in,
|
||||
wr_en,
|
||||
d_out );
|
||||
|
||||
input wire clk;
|
||||
input wire addr_0;
|
||||
input wire addr_1;
|
||||
input wire d_in;
|
||||
input wire wr_en;
|
||||
output wire d_out;
|
||||
|
||||
wire[1:0] addr;
|
||||
reg [3:0] mem;
|
||||
|
||||
assign addr = {addr_1, addr_0};
|
||||
assign d_out = (addr == 2'd0)? mem[0]:
|
||||
(addr == 2'd1)? mem[1]:
|
||||
(addr == 2'd2)? mem[2]: mem[3];
|
||||
|
||||
always@(posedge clk) begin
|
||||
if(wr_en) begin
|
||||
mem[addr] <= d_in;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
clk 0.5 0.5
|
||||
addr_0 0.5 0.2
|
||||
addr_1 0.5 0.2
|
||||
d_in 0.5 0.2
|
||||
wr_en 0.5 0.2
|
||||
int 0.5 0.2
|
||||
d_out 0.25 0.25
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
.model syn_spram_4x1
|
||||
.inputs clk addr_0 addr_1 d_in wr_en
|
||||
.outputs d_out
|
||||
|
||||
.subckt spram_4x1 clk=clk addr[0]=addr_0 addr[1]=addr_1 d_in=d_in wr_en=wr_en d_out=int
|
||||
|
||||
.latch int d_out re clk 0
|
||||
|
||||
|
||||
.end
|
||||
|
||||
.model spram_4x1
|
||||
.blackbox
|
||||
.inputs clk addr[0] addr[1] d_in wr_en
|
||||
.outputs d_out
|
||||
.end
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/////////////////////////////////////////
|
||||
// Functionality: 4x1 memory async read
|
||||
// Author: Aurelien Alacchi
|
||||
////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module syn_spram_4x1(
|
||||
clk,
|
||||
addr_0,
|
||||
addr_1,
|
||||
d_in,
|
||||
wr_en,
|
||||
d_out );
|
||||
|
||||
input wire clk;
|
||||
input wire addr_0;
|
||||
input wire addr_1;
|
||||
input wire d_in;
|
||||
input wire wr_en;
|
||||
output reg d_out;
|
||||
|
||||
wire[1:0] addr;
|
||||
wire tmp;
|
||||
reg [3:0] mem;
|
||||
|
||||
assign addr = {addr_1, addr_0};
|
||||
assign tmp = (addr == 2'd0)? mem[0]:
|
||||
(addr == 2'd1)? mem[1]:
|
||||
(addr == 2'd2)? mem[2]: mem[3];
|
||||
|
||||
always@(posedge clk) begin
|
||||
if(wr_en) begin
|
||||
mem[addr] <= d_in;
|
||||
end
|
||||
d_out <= tmp;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k6_N10_40nm.xml
|
||||
- General purpose logic block
|
||||
- K = 6, N = 10, I = 40
|
||||
- Single mode
|
||||
- Routing architecture
|
||||
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="input" prefix="sel" size="1"/>
|
||||
<port type="input" prefix="selb" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="16"/>
|
||||
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="QN" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="spram_4x1" prefix="spram_4x1" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/spram_4x1.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/spram_4x1.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="addr" lib_name="addr" size="2"/>
|
||||
<port type="input" prefix="d_in" lib_name="d_in" size="1"/>
|
||||
<port type="input" prefix="wr_en" lib_name="wr_en" size="1"/>
|
||||
<port type="output" prefix="d_out" lib_name="d_out" size="1"/>
|
||||
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFR"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
|
||||
<pb_type name="clb.fle[physical].fabric.spram_4x1" circuit_model_name="spram_4x1"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:2]"/>
|
||||
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<pb_type name="clb.fle[lutram].lutram.spram_4x1" physical_pb_type_name="clb.fle[physical].fabric.spram_4x1"/>
|
||||
<pb_type name="clb.fle[lutram].lutram.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<!-- Binding operating pb_types in mode 'ble4' -->
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// SPRAM 4x1 for implementation in LUT4-RAM
|
||||
// Asynchronous reading
|
||||
|
||||
module spram_4x1 (
|
||||
input clk,
|
||||
input[1:0] addr,
|
||||
input d_in,
|
||||
input wr_en,
|
||||
output d_out );
|
||||
|
||||
reg[3:0] mem;
|
||||
|
||||
assign d_out = mem[addr];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(wr_en) begin
|
||||
mem[addr] <= d_in;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -12,7 +12,11 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
|||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
||||
# Note: no need to assign activity file when you used a fixed number
|
||||
# of clock cycles in simulation settings
|
||||
# Also, ACE2 does not support multiple clocks
|
||||
# Therefore, activity file is not recommended for multi-clock fabric/implementations
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
|
|
|||
|
|
@ -409,7 +409,7 @@ def run_single_script(s, eachJob, job_list):
|
|||
with open(logfile, 'w+') as output:
|
||||
output.write("* "*20 + '\n')
|
||||
output.write("RunDirectory : %s\n" % os.getcwd())
|
||||
command = [gc["python_path"], gc["script_default"]] + \
|
||||
command = [os.getenv('PYTHON_EXEC', gc["python_path"]), gc["script_default"]] + \
|
||||
eachJob["commands"]
|
||||
output.write(" ".join(command) + '\n')
|
||||
output.write("* "*20 + '\n')
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_lutram_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
#
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/asyn_spram_4x1/asyn_spram_4x1.blif
|
||||
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/syn_spram_4x1/syn_spram_4x1.blif
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = and2_or2
|
||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
|
||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
|
||||
bench1_top = asyn_spram_4x1
|
||||
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/asyn_spram_4x1/asyn_spram_4x1.act
|
||||
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/asyn_spram_4x1/asyn_spram_4x1.v
|
||||
bench2_top = syn_spram_4x1
|
||||
bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/syn_spram_4x1/syn_spram_4x1.act
|
||||
bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/syn_spram_4x1/syn_spram_4x1.v
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
|
|
@ -0,0 +1,539 @@
|
|||
<!--
|
||||
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
|
||||
|
||||
- 40 nm technology
|
||||
- General purpose logic block:
|
||||
K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
|
||||
with optionally registered outputs with 4x1 bits SPRAM for dispersed memory functions.
|
||||
- This architecture ONLY MIMICS LUT-RAM FUNCTIONALITY
|
||||
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
|
||||
|
||||
Details on Modelling:
|
||||
|
||||
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
|
||||
|
||||
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
|
||||
-->
|
||||
<architecture>
|
||||
<!--
|
||||
ODIN II specific config begins
|
||||
Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
||||
".model [type_of_block]") that this architecture supports.
|
||||
|
||||
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||
already special structures in blif (.names, .input, .output, and .latch)
|
||||
that describe them.
|
||||
-->
|
||||
<models>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="frac_lut4">
|
||||
<input_ports>
|
||||
<port name="in"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="lut3_out"/>
|
||||
<port name="lut4_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="spram_4x1">
|
||||
<input_ports>
|
||||
<port name="wr_en" clock="clk"/>
|
||||
<port name="addr" clock="clk"/>
|
||||
<port name="d_in" clock="clk"/>
|
||||
<port name="clk" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="d_out" clock="clk"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<tile name="io" capacity="1" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io.outpad io.inpad</loc>
|
||||
<loc side="top">io.outpad io.inpad</loc>
|
||||
<loc side="right">io.outpad io.inpad</loc>
|
||||
<loc side="bottom">io.outpad io.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<tile name="clb" area="53894">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I" num_pins="12" equivalent="full"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<!--pinlocations pattern="spread"/-->
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">clb.clk</loc>
|
||||
<loc side="top"></loc>
|
||||
<loc side="right">clb.O[3:0] clb.I[5:0]</loc>
|
||||
<loc side="bottom">clb.O[7:4] clb.I[11:6]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout tileable="true">
|
||||
<auto_layout aspect_ratio="1.0">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</auto_layout>
|
||||
<fixed_layout name="2x2" width="4" height="4">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="4x4" width="6" height="6">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||
lined up with Stratix IV.
|
||||
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||
by 2.5x when looking up in Jeff's tables.
|
||||
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||
proposed FPGA, and which is also 40 nm
|
||||
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||
4x minimum drive strength buffer. -->
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
||||
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
||||
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
||||
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
||||
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
||||
2.5x when looking up in Jeff's tables.
|
||||
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
|
||||
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="0"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<complexblocklist>
|
||||
<!-- Define I/O pads begin -->
|
||||
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||
<pb_type name="io">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<!-- A mode denotes the physical implementation of an I/O
|
||||
This mode will be not packable but is mainly used for fabric verilog generation
|
||||
-->
|
||||
<mode name="physical" disabled_in_pack="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
</direct>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
|
||||
<!-- IOs can operate as either inputs or outputs.
|
||||
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||
today and that is when you timing analyze them.
|
||||
-->
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||||
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||||
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||||
-->
|
||||
<!-- Place I/Os on the sides of the FPGA -->
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<!-- Define I/O pads ends -->
|
||||
<!-- Define general purpose logic block (CLB) begin -->
|
||||
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
||||
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
||||
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
||||
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
||||
block. Note that the crossbar / local interconnect is considered part of the logic block
|
||||
area in this analysis. That is a lower proportion of of routing area than most academics
|
||||
assume, but note that the total routing area really includes the crossbar, which would push
|
||||
routing area up significantly, we estimate into the ~70% range.
|
||||
-->
|
||||
<pb_type name="clb">
|
||||
<input name="I" num_pins="12" equivalent="full"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Describe fracturable logic element.
|
||||
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||
The outputs of the fracturable logic element can be optionally registered
|
||||
-->
|
||||
<pb_type name="fle" num_pb="4">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Physical mode definition begin (physical implementation of the fle) -->
|
||||
<mode name="physical" disabled_in_pack="true">
|
||||
<pb_type name="fabric" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="lut3_out" num_pins="2"/>
|
||||
<output name="lut4_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
|
||||
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
|
||||
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
|
||||
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<!-- Define spram_4x1 -->
|
||||
<pb_type name="spram_4x1" blif_model=".subckt spram_4x1" num_pb="1">
|
||||
<input name="wr_en" num_pins="1"/>
|
||||
<input name="addr" num_pins="2"/>
|
||||
<input name="d_in" num_pins="1"/>
|
||||
<output name="d_out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="509e-12" port="spram_4x1.wr_en" clock="clk"/>
|
||||
<T_setup value="509e-12" port="spram_4x1.addr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="spram_4x1.d_in" clock="clk"/>
|
||||
<T_clock_to_Q max="1.234e-9" port="spram_4x1.d_out" clock="clk"/>
|
||||
<power method="pin-toggle">
|
||||
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||||
<static_power power_per_instance="0.0"/>
|
||||
</power>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
|
||||
<direct name="direct_mem_en" input="fabric.in[0]" output="spram_4x1.wr_en"/>
|
||||
<direct name="direct_mem_in" input="fabric.in[3]" output="spram_4x1.d_in"/>
|
||||
<direct name="direct_mem_addr" input="fabric.in[2:1]" output="spram_4x1.addr"/>
|
||||
<complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/>
|
||||
<complete name="direct_mem_clk" input="fabric.clk" output="spram_4x1.clk"/>
|
||||
<mux name="mux1" input="frac_logic.out[0:0] spram_4x1.d_out" output="ff[0:0].D">
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
|
||||
<delay_constant max="45e-12" in_port="spram_4x1.d_out" out_port="ff[0:0].D"/>
|
||||
</mux>
|
||||
<mux name="mux2" input="frac_logic.out[1:1] spram_4x1.d_out" output="ff[1:1].D">
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
|
||||
<delay_constant max="45e-12" in_port="spram_4x1.d_out" out_port="ff[1:1].D"/>
|
||||
</mux>
|
||||
<mux name="mux3" input="spram_4x1.d_out ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
|
||||
</mux>
|
||||
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||
<direct name="direct3" input="fabric.out" output="fle.out"/>
|
||||
<direct name="direct5" input="fle.clk" output="fabric.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||
<!-- Dual 3-LUT mode definition begin -->
|
||||
<mode name="n2_lut3">
|
||||
<pb_type name="lut3inter" num_pb="1">
|
||||
<input name="in" num_pins="3"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="ble3" num_pb="2">
|
||||
<input name="in" num_pins="3"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define the LUT -->
|
||||
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="3" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define the flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
|
||||
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
|
||||
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
|
||||
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
|
||||
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
|
||||
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
|
||||
<direct name="direct2" input="lut3inter.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Dual 3-LUT mode definition end -->
|
||||
<!-- BEGIN lutram mode -->
|
||||
<mode name="lutram">
|
||||
<pb_type name="lutram" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="spram_4x1" blif_model=".subckt spram_4x1" num_pb="1">
|
||||
<input name="wr_en" num_pins="1"/>
|
||||
<input name="addr" num_pins="2"/>
|
||||
<input name="d_in" num_pins="1"/>
|
||||
<output name="d_out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="509e-12" port="spram_4x1.wr_en" clock="clk"/>
|
||||
<T_setup value="509e-12" port="spram_4x1.addr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="spram_4x1.d_in" clock="clk"/>
|
||||
<T_clock_to_Q max="1.234e-9" port="spram_4x1.d_out" clock="clk"/>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="clock_mem" input="lutram.clk" output="spram_4x1.clk"/>
|
||||
<direct name="mem_wr_en" input="lutram.in[0]" output="spram_4x1.wr_en"/>
|
||||
<direct name="mem_addr" input="lutram.in[2:1]" output="spram_4x1.addr"/>
|
||||
<direct name="mem_d_in" input="lutram.in[3]" output="spram_4x1.d_in"/>
|
||||
<complete name="ff_d" input="spram_4x1.d_out" output="ff.D"/>
|
||||
<complete name="clock_ff" input="lutram.clk" output="ff.clk"/>
|
||||
<mux name="mem_out_0" input="ff[0].Q spram_4x1.d_out" output="lutram.out[0]">
|
||||
<delay_constant max="25e-12" in_port="spram_4x1.d_out" out_port="lutram.out[0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="lutram.out"/>
|
||||
</mux>
|
||||
<mux name="mem_out_1" input="ff[1].Q spram_4x1.d_out" output="lutram.out[1]">
|
||||
<delay_constant max="25e-12" in_port="spram_4x1.d_out" out_port="lutram.out[1]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="lutram.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[3:0]" output="lutram.in"/>
|
||||
<direct name="direct3" input="fle.clk" output="lutram.clk"/>
|
||||
<direct name="direct4" input="lutram.out" output="fle.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- 4-LUT mode definition begin -->
|
||||
<mode name="n1_lut4">
|
||||
<!-- Define 4-LUT mode -->
|
||||
<pb_type name="ble4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
397e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
||||
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- 4-LUT mode definition end -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||||
The delays below come from Stratix IV. the delay through a connection block
|
||||
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||
delay within the crossbar is 95 ps.
|
||||
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||||
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||
to get the part that should be marked on the crossbar. -->
|
||||
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||
naive specification).
|
||||
-->
|
||||
<direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
|
||||
<direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
|
||||
</interconnect>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- Place this general purpose logic block in any unspecified column -->
|
||||
</pb_type>
|
||||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
docker run -it --rm -v "%cd%":/localfile/OpenFPGA -w="/localfile/OpenFPGA" goreganesh/open_fpga bash
|
||||
pause
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
#!/bin/bash
|
||||
docker run -it --rm -v "${PWD}":/root/dev/OpenFPGA -w="/root/dev/OpenFPGA" goreganesh/open_fpga bash
|
||||
pause
|
||||
2
yosys
2
yosys
|
|
@ -1 +1 @@
|
|||
Subproject commit 14b993449d5b6e37d69ff523356d05941a78b66e
|
||||
Subproject commit ad9dbd4be89bf30724b744693336ab21639cd461
|
||||
Loading…
Reference in New Issue