diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 327a51f40..9fe0a4ad6 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -147,6 +147,34 @@ static int route_clock_tree_rr_graph( des_spine_level, ipin, des_spine_direction); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); + /* Internal drivers may appear at the switch point. Check if there are any defined and related rr_node found as incoming edges. If the global net is mapped to the internal driver, use it as the previous node */ + size_t use_int_driver = 0; + for (!spine_switch_point_internal_drivers(ispine, switch_point_id).empty() && tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(ipin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + use_int_driver++; + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR("Found %lu internal drivers for the switching point (%lu, %lu) for spine '%s'!\n Expect only 1!\n", use_int_driver, src_coord.x(), src_coord.y(), clk_ntwk.spine_name(ispine).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (use_int_driver == 1) { + continue; /* Used internal driver, early pass */ + } vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the