diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c
index b1eb28306..83fcf2121 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c
@@ -38,6 +38,7 @@
 #include "fpga_x2p_lut_utils.h"
 #include "fpga_x2p_bitstream_utils.h"
 #include "fpga_x2p_pbtypes_utils.h"
+#include "fpga_x2p_naming.h"
 #include "fpga_x2p_globals.h"
 
 /* Make sure the edge has only one input pin and output pin*/
@@ -1331,6 +1332,25 @@ t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type,
   return ret;
 }
 
+/********************************************************************
+ * Add the port-to-port mapping between a pb_type and its linked circuit model 
+ * This function is mainly used to create instance of the module for a pb_type
+ *******************************************************************/
+void generate_pb_type_circuit_port2port_name_map(std::map<std::string, BasicPort>& port2port_name_map,
+                                                 t_pb_type* cur_pb_type,
+                                                 const CircuitLibrary& circuit_lib) {
+  for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) {
+    t_port* pb_type_port = &(cur_pb_type->ports[iport]);
+    /* Must have a linked circuit model port */
+    VTR_ASSERT( CircuitPortId::INVALID() != pb_type_port->circuit_model_port);
+    std::string module_port_name = circuit_lib.port_lib_name(pb_type_port->circuit_model_port);
+    /* Generate the module port name of pb_type */
+    BasicPort instance_port(generate_pb_type_port_name(pb_type_port), circuit_lib.port_size(pb_type_port->circuit_model_port));
+    /* Create the port of primitive model */
+    port2port_name_map[module_port_name] = instance_port; 
+  } 
+}
+
 /********************************************************************
  * Return a list of ports of a pb_type which matches the ports defined
  * in its linked circuit model 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h
index ee5db00f4..d7c969efa 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h
@@ -3,6 +3,9 @@
 
 /* Only include header files those are required by the data types in the following function declaration */
 #include <vector>
+#include <map>
+#include "device_port.h"
+#include "circuit_library.h"
 #include "fpga_x2p_types.h"
 #include "fpga_x2p_bitstream_utils.h"
 
@@ -103,6 +106,10 @@ void map_clb_pins_to_pb_graph_pins();
 t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type,
                                                  t_spice_model_port* spice_model_port);
 
+void generate_pb_type_circuit_port2port_name_map(std::map<std::string, BasicPort>& port2port_name_map,
+                                                 t_pb_type* cur_pb_type,
+                                                 const CircuitLibrary& circuit_lib);
+
 std::vector<t_port*> find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type,
                                                                       enum e_spice_model_port_type port_type);
 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp
index f4c719900..dd6822c35 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp
@@ -149,13 +149,40 @@ void print_verilog_primitive_block(std::fstream& fp,
   print_verilog_module_declaration(fp, module_manager, primitive_module);
   /* Finish printing ports */
 
-  /* TODO: Create local wires as configuration bus */
+  /* Find the module id in the module manager */
+  ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model));
+  VTR_ASSERT(ModuleId::INVALID() != logic_module);
+  size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); 
 
-  /* TODO: Create a bus wire for the inputs of the LUT */
+  /* Local wires for memory configurations */
+  print_verilog_comment(fp, std::string("---- BEGIN local configuration bus ----"));
+  print_verilog_local_config_bus(fp, circuit_lib.model_name(primitive_model), cur_sram_orgz_info->type, logic_instance_id, num_config_bits);
+  print_verilog_comment(fp, std::string("---- END local configuration bus ----"));
 
-  /* TODO: Instanciate LUT MUX module */
+  /* Add an empty line as a splitter */
+  fp << std::endl;
 
-  /* TODO: Instanciate associated memory module for the LUT */
+  /* TODO: Instanciate the logic module */
+  /* Create port-to-port map */
+  std::map<std::string, BasicPort> logic_port2port_name_map;
+  /* Link the logic model ports to pb_type ports */
+  generate_pb_type_circuit_port2port_name_map(logic_port2port_name_map, primitive_pb_graph_node->pb_type, circuit_lib);
+  /* TODO: Link both regular and mode-select SRAM ports */
+
+  /* Print an instance of the logic Module */
+  print_verilog_comment(fp, std::string("----- BEGIN Instanciation of " + circuit_lib.model_name(primitive_model) + " -----"));
+  print_verilog_module_instance(fp, module_manager, primitive_module, logic_module, logic_port2port_name_map, use_explicit_mapping);
+  print_verilog_comment(fp, std::string("----- END Instanciation of " + circuit_lib.model_name(primitive_model) + " -----"));
+  fp << std::endl;
+  /* IMPORTANT: this update MUST be called after the instance outputting!!!!
+   * update the module manager with the relationship between the parent and child modules 
+   */
+  module_manager.add_child_module(primitive_module, logic_module);
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* TODO: Instanciate associated memory module */
 
   /* Print an end to the Verilog module */
   print_verilog_module_end(fp, module_manager.module_name(primitive_module));
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
index 141a2c367..d582c59bd 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
@@ -867,7 +867,6 @@ void print_verilog_local_sram_wires(std::fstream& fp,
  *               +----------+  +----------+     +----------+
  *     
  *********************************************************************/
-static 
 void print_verilog_local_config_bus(std::fstream& fp, 
                                     const std::string& prefix,
                                     const e_sram_orgz& sram_orgz_type,
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h
index e53ac0a40..5e390ed02 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h
@@ -90,6 +90,12 @@ void print_verilog_local_sram_wires(std::fstream& fp,
                                     const e_sram_orgz sram_orgz_type,
                                     const size_t& port_size);
 
+void print_verilog_local_config_bus(std::fstream& fp, 
+                                    const std::string& prefix,
+                                    const e_sram_orgz& sram_orgz_type,
+                                    const size_t& instance_id,
+                                    const size_t& num_conf_bits); 
+
 void print_verilog_mux_config_bus(std::fstream& fp, 
                                   const CircuitLibrary& circuit_lib,
                                   const CircuitModelId& mux_model,