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Update dff.v

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Kishor 2021-09-16 13:13:32 +05:30 committed by GitHub
parent ae00f15b05
commit 9c4b013cb2
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1 changed files with 4 additions and 2 deletions
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openfpga_flow/openfpga_cell_library/verilog/dff.v
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@ -260,7 +260,8 @@ module MULTI_MODE_DFFSRQ (
); );
wire post_set = mode[1] ? ~SET : SET; wire post_set = mode[1] ? ~SET : SET;
wire post_reset = mode[0] ? ~RST : RST; //wire post_reset = mode[0] ? ~RST : RST;
wire post_rst = mode[0] ? ~RST : RST;
DFFSRQ FF_CORE (.SET(post_set), DFFSRQ FF_CORE (.SET(post_set),
.RST(post_rst), .RST(post_rst),
@ -284,7 +285,8 @@ module MULTI_MODE_DFFRQ (
input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
); );
wire post_reset = mode ? ~RST : RST; //wire post_reset = mode ? ~RST : RST;
wire post_rst = mode ? ~RST : RST;
DFFRQ FF_CORE (.RST(post_rst), DFFRQ FF_CORE (.RST(post_rst),
.CK(CK), .CK(CK),