From 9bcaa820ae850b785f21ba5b4f0d12749041f254 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 3 Jun 2021 16:18:07 -0600 Subject: [PATCH] [Doc] Update documentation for the new command 'write_full_testbench' --- .../manual/file_formats/fabric_bitstream.rst | 2 +- .../fpga_verilog_commands.rst | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/file_formats/fabric_bitstream.rst b/docs/source/manual/file_formats/fabric_bitstream.rst index 11faca959..92e11f24e 100644 --- a/docs/source/manual/file_formats/fabric_bitstream.rst +++ b/docs/source/manual/file_formats/fabric_bitstream.rst @@ -5,7 +5,7 @@ Fabric-dependent Bitstream .. _file_formats_fabric_bitstream_plain_text: -Plain text (.txt) +Plain text (.bit) ~~~~~~~~~~~~~~~~~ This file format is designed to be directly loaded to an FPGA fabric. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 11c64b45f..c22d5aa73 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -87,3 +87,39 @@ write_verilog_testbench .. option:: --explicit_port_mapping Use explicit port mapping when writing the Verilog netlists + +write_full_testbench +~~~~~~~~~~~~~~~~~~~~~~~ + + Write the full testbench for FPGA fabric in Verilog format + + .. option:: --file or -f + + The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench`` + + .. option:: --bitstream + + The bitstream file to be loaded to the full testbench, which should be in the same file format that OpenFPGA can outputs (See detailes in :ref:`file_formats_fabric_bitstream_plain_text`). For example, ``--bitstream and2.bit`` + + .. option:: --fabric_netlist_file_path + + Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v`` + + .. option:: --reference_benchmark_file_path + + Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. option:: --pin_constraints_file or -pcf + + Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml`` + Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`. + + .. option:: --explicit_port_mapping + + Use explicit port mapping when writing the Verilog netlists + + .. option:: --include_signal_init + + Output signal initialization to Verilog testbench to smooth convergence in HDL simulation + +