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Merge pull request #1208 from lnis-uofu/xt_vtr_upgrade 

Upgrade VTR to latest version
This commit is contained in:
tangxifan 2023-06-08 18:07:48 -07:00 committed by GitHub
parent f1531c8a1f 1ef8eed589
commit 9b2555a59a
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
32 changed files with 1432 additions and 1372 deletions
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2
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -396,7 +396,7 @@ static void try_find_and_add_clock_track2ipin_node(
const e_side& pin_side, const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) {
t_physical_tile_type_ptr grid_type =
grids[grid_coord.x()][grid_coord.y()].type;
grids.get_physical_type(grid_coord.x(), grid_coord.y());
for (std::string tap_pin_name :
clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) {
/* tap pin name could be 'io[5:5].a2f[0]' */

2
openfpga/src/annotation/vpr_placement_annotation.cpp
View File

@ -32,7 +32,7 @@ void VprPlacementAnnotation::init_mapped_blocks(const DeviceGrid& grids) {
for (size_t x = 0; x < grids.width(); ++x) {
for (size_t y = 0; y < grids.height(); ++y) {
/* Deposit invalid ids and we will fill later */
blocks_[x][y].resize(grids[x][y].type->capacity,
blocks_[x][y].resize(grids.get_physical_type(x, y)->capacity,
ClusterBlockId::INVALID());
}
}

10
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -39,7 +39,8 @@ static void update_cluster_pin_with_post_routing_results(
const e_side& border_side, const size_t& z, const bool& verbose) {
/* Handle each pin */
auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
auto physical_tile = device_ctx.grid[grid_coord.x()][grid_coord.y()].type;
auto physical_tile =
device_ctx.grid.get_physical_type(grid_coord.x(), grid_coord.y());
for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
/* Get the ptc num for the pin in rr_graph, we need t consider the z offset
@ -195,7 +196,7 @@ void update_pb_pin_with_post_routing_results(
for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) {
for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) {
/* Bypass the EMPTY tiles */
if (true == is_empty_type(device_ctx.grid[x][y].type)) {
if (true == is_empty_type(device_ctx.grid.get_physical_type(x, y))) {
continue;
}
/* Get the mapped blocks to this grid */
@ -222,9 +223,10 @@ void update_pb_pin_with_post_routing_results(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coord : io_coordinates[io_side]) {
t_physical_tile_type_ptr phy_tile_type =
device_ctx.grid.get_physical_type(io_coord.x(), io_coord.y());
/* Bypass EMPTY grid */
if (true ==
is_empty_type(device_ctx.grid[io_coord.x()][io_coord.y()].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Get the mapped blocks to this grid */

16
openfpga/src/fabric/build_fabric_io_location_map.cpp
View File

@ -50,15 +50,17 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager,
ModuleId child = module_manager.io_children(top_module)[ichild];
vtr::Point<int> coord =
module_manager.io_child_coordinates(top_module)[ichild];
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(coord.x(), coord.y());
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[coord.x()][coord.y()].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[coord.x()][coord.y()].width_offset) ||
(0 < grids[coord.x()][coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(coord.x(), coord.y())) ||
(0 < grids.get_height_offset(coord.x(), coord.y()))) {
continue;
}
@ -69,14 +71,14 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager,
/* MUST DO: register in io location mapping!
* I/O location mapping is a critical look-up for testbench generators
*/
if (size_t(grids[coord.x()][coord.y()].type->capacity) !=
if (size_t(phy_tile_type->capacity) !=
module_manager.io_children(child).size()) {
VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
grids[coord.x()][coord.y()].type->name, coord.x(), coord.y(),
grids[coord.x()][coord.y()].type->capacity,
phy_tile_type->name, coord.x(), coord.y(),
phy_tile_type->capacity,
module_manager.io_children(child).size());
}
VTR_ASSERT(size_t(grids[coord.x()][coord.y()].type->capacity) ==
VTR_ASSERT(size_t(phy_tile_type->capacity) ==
module_manager.io_children(child).size());
for (size_t isubchild = 0;
isubchild < module_manager.io_children(child).size(); ++isubchild) {

10
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -76,9 +76,8 @@ std::string generate_sb_module_grid_port_name(
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node);
t_physical_tile_type_ptr physical_tile =
vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)]
.type;
t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type(
rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node));
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info =
@ -111,9 +110,8 @@ std::string generate_cb_module_grid_port_name(
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node);
t_physical_tile_type_ptr physical_tile =
vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)]
.type;
t_physical_tile_type_ptr physical_tile = vpr_device_grid.get_physical_type(
rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node));
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info =

52
openfpga/src/fabric/build_top_module.cpp
View File

@ -108,22 +108,23 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(io_coordinate.x(), io_coordinate.y());
/* Bypass EMPTY grid */
if (true ==
is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset) ||
(0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) ||
(0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) {
/* Find the root of this grid, the instance id should be valid.
* We just copy it here
*/
vtr::Point<size_t> root_grid_coord(
io_coordinate.x() -
grids[io_coordinate.x()][io_coordinate.y()].width_offset,
grids.get_width_offset(io_coordinate.x(), io_coordinate.y()),
io_coordinate.y() -
grids[io_coordinate.x()][io_coordinate.y()].height_offset);
grids.get_height_offset(io_coordinate.x(), io_coordinate.y()));
VTR_ASSERT(size_t(-1) !=
grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
grid_instance_ids[io_coordinate.x()][io_coordinate.y()] =
@ -133,10 +134,8 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
/* Add a grid module to top_module*/
grid_instance_ids[io_coordinate.x()][io_coordinate.y()] =
add_top_module_grid_instance(
module_manager, top_module,
grids[io_coordinate.x()][io_coordinate.y()].type, io_side,
io_coordinate);
add_top_module_grid_instance(module_manager, top_module, phy_tile_type,
io_side, io_coordinate);
}
}
@ -148,18 +147,20 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
*/
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(ix, iy);
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[ix][iy].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[ix][iy].width_offset) ||
(0 < grids[ix][iy].height_offset)) {
if ((0 < grids.get_width_offset(ix, iy)) ||
(0 < grids.get_height_offset(ix, iy))) {
/* Find the root of this grid, the instance id should be valid.
* We just copy it here
*/
vtr::Point<size_t> root_grid_coord(ix - grids[ix][iy].width_offset,
iy - grids[ix][iy].height_offset);
vtr::Point<size_t> root_grid_coord(
ix - grids.get_width_offset(ix, iy),
iy - grids.get_height_offset(ix, iy));
VTR_ASSERT(size_t(-1) !=
grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
grid_instance_ids[ix][iy] =
@ -169,7 +170,7 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
/* Add a grid module to top_module*/
vtr::Point<size_t> grid_coord(ix, iy);
grid_instance_ids[ix][iy] = add_top_module_grid_instance(
module_manager, top_module, grids[ix][iy].type, NUM_SIDES, grid_coord);
module_manager, top_module, phy_tile_type, NUM_SIDES, grid_coord);
}
}
@ -324,18 +325,18 @@ static void add_top_module_io_children(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coord : io_coordinates[io_side]) {
t_physical_tile_type_ptr grid_type =
grids.get_physical_type(io_coord.x(), io_coord.y());
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[io_coord.x()][io_coord.y()].type)) {
if (true == is_empty_type(grid_type)) {
continue;
}
/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coord.x()][io_coord.y()].width_offset) ||
(0 < grids[io_coord.x()][io_coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(io_coord.x(), io_coord.y())) ||
(0 < grids.get_height_offset(io_coord.x(), io_coord.y()))) {
continue;
}
/* Find the module name for this type of grid */
t_physical_tile_type_ptr grid_type =
grids[io_coord.x()][io_coord.y()].type;
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_module_name = generate_grid_block_module_name(
grid_module_name_prefix, std::string(grid_type->name),
@ -393,17 +394,18 @@ static void add_top_module_io_children(
/* Now walk through the coordinates */
for (vtr::Point<size_t> coord : coords) {
t_physical_tile_type_ptr grid_type =
grids.get_physical_type(coord.x(), coord.y());
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[coord.x()][coord.y()].type)) {
if (true == is_empty_type(grid_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[coord.x()][coord.y()].width_offset) ||
(0 < grids[coord.x()][coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(coord.x(), coord.y())) ||
(0 < grids.get_height_offset(coord.x(), coord.y()))) {
continue;
}
/* Find the module name for this type of grid */
t_physical_tile_type_ptr grid_type = grids[coord.x()][coord.y()].type;
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_module_name = generate_grid_block_module_name(
grid_module_name_prefix, std::string(grid_type->name),

33
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -127,7 +127,7 @@ static void add_top_module_nets_connect_grids_and_sb(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
t_physical_tile_type_ptr grid_type_descriptor =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
size_t src_grid_pin_width =
grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height =
@ -301,7 +301,7 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
t_physical_tile_type_ptr grid_type_descriptor =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
size_t src_grid_pin_width =
grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height =
@ -520,7 +520,7 @@ static void add_top_module_nets_connect_grids_and_cb(
size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node);
t_physical_tile_type_ptr grid_type_descriptor =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
size_t sink_grid_pin_width =
grid_type_descriptor->pin_width_offset[sink_grid_pin_index];
size_t sink_grid_pin_height =
@ -859,7 +859,7 @@ static int build_top_module_global_net_for_given_grid_module(
const vtr::Point<size_t>& grid_coordinate, const e_side& border_side,
const vtr::Matrix<size_t>& grid_instance_ids) {
t_physical_tile_type_ptr physical_tile =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
/* Find the module name for this type of grid */
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_module_name = generate_grid_block_module_name(
@ -1038,18 +1038,20 @@ static int build_top_module_global_net_from_grid_modules(
/* Spot the port from child modules from core grids */
for (size_t ix = start_coord.x(); ix < end_coord.x(); ++ix) {
for (size_t iy = start_coord.y(); iy < end_coord.y(); ++iy) {
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(ix, iy);
/* Bypass EMPTY tiles */
if (true == is_empty_type(grids[ix][iy].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[ix][iy].width_offset) ||
(0 < grids[ix][iy].height_offset)) {
if ((0 < grids.get_width_offset(ix, iy)) ||
(0 < grids.get_height_offset(ix, iy))) {
continue;
}
/* Bypass the tiles whose names do not match */
if (std::string(grids[ix][iy].type->name) != tile_name) {
if (std::string(phy_tile_type->name) != tile_name) {
continue;
}
@ -1067,22 +1069,23 @@ static int build_top_module_global_net_from_grid_modules(
/* Walk through all the grids on the perimeter, which are I/O grids */
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(io_coordinate.x(), io_coordinate.y());
/* Bypass EMPTY grid */
if (true ==
is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset) ||
(0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
if ((0 <
grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) ||
(0 <
grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) {
continue;
}
/* Bypass the tiles whose names do not match */
if (std::string(
grids[io_coordinate.x()][io_coordinate.y()].type->name) !=
tile_name) {
if (std::string(phy_tile_type->name) != tile_name) {
continue;
}

8
openfpga/src/fabric/build_top_module_directs.cpp
View File

@ -47,7 +47,7 @@ static void add_module_nets_tile_direct_connection(
vtr::Point<size_t> src_clb_coord =
tile_direct.from_tile_coordinate(tile_direct_id);
t_physical_tile_type_ptr src_grid_type =
grids[src_clb_coord.x()][src_clb_coord.y()].type;
grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y());
e_side src_grid_border_side =
find_grid_border_side(device_size, src_clb_coord);
std::string src_module_name_prefix(GRID_MODULE_NAME_PREFIX);
@ -64,7 +64,7 @@ static void add_module_nets_tile_direct_connection(
vtr::Point<size_t> des_clb_coord =
tile_direct.to_tile_coordinate(tile_direct_id);
t_physical_tile_type_ptr sink_grid_type =
grids[des_clb_coord.x()][des_clb_coord.y()].type;
grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y());
e_side sink_grid_border_side =
find_grid_border_side(device_size, des_clb_coord);
std::string sink_module_name_prefix(GRID_MODULE_NAME_PREFIX);
@ -114,7 +114,7 @@ static void add_module_nets_tile_direct_connection(
size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id);
t_physical_tile_type_ptr src_grid_type_descriptor =
grids[src_clb_coord.x()][src_clb_coord.y()].type;
grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y());
size_t src_pin_width =
src_grid_type_descriptor->pin_width_offset[src_tile_pin];
size_t src_pin_height =
@ -148,7 +148,7 @@ static void add_module_nets_tile_direct_connection(
size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id);
t_physical_tile_type_ptr sink_grid_type_descriptor =
grids[des_clb_coord.x()][des_clb_coord.y()].type;
grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y());
size_t sink_pin_width =
sink_grid_type_descriptor->pin_width_offset[src_tile_pin];
size_t sink_pin_height =

6
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -191,7 +191,7 @@ static void organize_top_module_tile_memory_modules(
/* Find the module name for this type of grid */
t_physical_tile_type_ptr grid_type =
grids[tile_coord.x()][tile_coord.y()].type;
grids.get_physical_type(tile_coord.x(), tile_coord.y());
/* Skip EMPTY Grid */
if (true == is_empty_type(grid_type)) {
@ -199,8 +199,8 @@ static void organize_top_module_tile_memory_modules(
}
/* Skip width > 1 or height > 1 Grid, which should already been processed when
* offset=0 */
if ((0 < grids[tile_coord.x()][tile_coord.y()].width_offset) ||
(0 < grids[tile_coord.x()][tile_coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(tile_coord.x(), tile_coord.y())) ||
(0 < grids.get_height_offset(tile_coord.x(), tile_coord.y()))) {
return;
}

6
openfpga/src/fabric/build_top_module_utils.cpp
View File

@ -28,10 +28,12 @@ std::string generate_grid_block_module_name_in_top_module(
/* Determine if the grid locates at the border */
vtr::Point<size_t> device_size(grids.width(), grids.height());
e_side border_side = find_grid_border_side(device_size, grid_coord);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(grid_coord.x(), grid_coord.y());
return generate_grid_block_module_name(
prefix, std::string(grids[grid_coord.x()][grid_coord.y()].type->name),
is_io_type(grids[grid_coord.x()][grid_coord.y()].type), border_side);
prefix, std::string(phy_tile_type->name), is_io_type(phy_tile_type),
border_side);
}
/********************************************************************

16
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -736,7 +736,7 @@ static void build_physical_block_bitstream(
const vtr::Point<size_t>& grid_coord, const e_side& border_side) {
/* Create a block for the grid in bitstream manager */
t_physical_tile_type_ptr grid_type =
grids[grid_coord.x()][grid_coord.y()].type;
grids.get_physical_type(grid_coord.x(), grid_coord.y());
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
/* Early exit if this parent module has no configurable child modules */
@ -831,12 +831,12 @@ void build_grid_bitstream(
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[ix][iy].type)) {
if (true == is_empty_type(grids.get_physical_type(ix, iy))) {
continue;
}
/* Skip width > 1 or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[ix][iy].width_offset) ||
(0 < grids[ix][iy].height_offset)) {
if ((0 < grids.get_width_offset(ix, iy)) ||
(0 < grids.get_height_offset(ix, iy))) {
continue;
}
/* Add a grid module to top_module*/
@ -859,13 +859,13 @@ void build_grid_bitstream(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
/* Bypass EMPTY grid */
if (true ==
is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
if (true == is_empty_type(grids.get_physical_type(io_coordinate.x(),
io_coordinate.y()))) {
continue;
}
/* Skip height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset) ||
(0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) ||
(0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) {
continue;
}
build_physical_block_bitstream(

6
openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
View File

@ -604,14 +604,14 @@ static void print_analysis_sdc_disable_unused_grid(
valid_file_stream(fp);
t_physical_tile_type_ptr grid_type =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
/* Bypass conditions for grids :
* 1. EMPTY type, which is by nature unused
* 2. Offset > 0, which has already been processed when offset = 0
*/
if ((true == is_empty_type(grid_type)) ||
(0 < grids[grid_coordinate.x()][grid_coordinate.y()].width_offset) ||
(0 < grids[grid_coordinate.x()][grid_coordinate.y()].height_offset)) {
(0 < grids.get_width_offset(grid_coordinate.x(), grid_coordinate.y())) ||
(0 < grids.get_height_offset(grid_coordinate.x(), grid_coordinate.y()))) {
return;
}

85
openfpga/src/tile_direct/build_tile_direct.cpp
View File

@ -168,7 +168,7 @@ static vtr::Point<size_t> find_grid_coordinate_given_type(
continue;
}
if (wanted_grid_type_name ==
std::string(grids[coord.x()][coord.y()].type->name)) {
std::string(grids.get_physical_type(coord.x(), coord.y())->name)) {
return coord;
}
}
@ -401,13 +401,15 @@ static void build_inner_column_row_tile_direct(
/* Walk through the device fabric and find the grid that fit the source */
for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
t_physical_tile_type_ptr from_phy_tile_type =
device_ctx.grid.get_physical_type(x, y);
/* Bypass empty grid */
if (true == is_empty_type(device_ctx.grid[x][y].type)) {
if (true == is_empty_type(from_phy_tile_type)) {
continue;
}
/* Bypass the grid that does not fit the from_tile name */
if (from_tile_name != std::string(device_ctx.grid[x][y].type->name)) {
if (from_tile_name != std::string(from_phy_tile_type->name)) {
continue;
}
@ -418,8 +420,8 @@ static void build_inner_column_row_tile_direct(
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid[x][y].type, device_ctx.grid[x][y].width_offset,
device_ctx.grid[x][y].height_offset, from_tile_port, from_side);
from_phy_tile_type, device_ctx.grid.get_width_offset(x, y),
device_ctx.grid.get_height_offset(x, y), from_tile_port, from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
continue;
@ -435,10 +437,11 @@ static void build_inner_column_row_tile_direct(
continue;
}
t_physical_tile_type_ptr to_phy_tile_type =
device_ctx.grid.get_physical_type(to_grid_coord.x(),
to_grid_coord.y());
/* Bypass the grid that does not fit the from_tile name */
if (to_tile_name !=
std::string(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()]
.type->name)) {
if (to_tile_name != std::string(to_phy_tile_type->name)) {
continue;
}
@ -448,11 +451,13 @@ static void build_inner_column_row_tile_direct(
*/
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
to_tile_port, to_side);
std::vector<size_t> to_pins =
find_physical_tile_pin_id(to_phy_tile_type,
device_ctx.grid.get_width_offset(
to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_height_offset(
to_grid_coord.x(), to_grid_coord.y()),
to_tile_port, to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
continue;
@ -589,13 +594,14 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()]
.width_offset,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()]
.height_offset,
from_tile_port, from_side);
std::vector<size_t> from_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_width_offset(
from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_height_offset(
from_grid_coord.x(), from_grid_coord.y()),
from_tile_port, from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
continue;
@ -619,11 +625,14 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
to_tile_port, to_side);
std::vector<size_t> to_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_width_offset(
to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_height_offset(
to_grid_coord.x(), to_grid_coord.y()),
to_tile_port, to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
continue;
@ -698,11 +707,14 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
from_tile_port, from_side);
std::vector<size_t> from_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_width_offset(
from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_height_offset(
from_grid_coord.x(), from_grid_coord.y()),
from_tile_port, from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
continue;
@ -726,11 +738,14 @@ static void build_inter_column_row_tile_direct(
*/
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
to_tile_port, to_side);
std::vector<size_t> to_pins =
find_physical_tile_pin_id(device_ctx.grid.get_physical_type(
to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_width_offset(
to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_height_offset(
to_grid_coord.x(), to_grid_coord.y()),
to_tile_port, to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
continue;

5
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -89,7 +89,7 @@ std::set<e_side> find_physical_io_tile_located_sides(
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
/* If located in center, we add a NUM_SIDES and finish */
if (physical_tile == grids[ix][iy].type) {
if (physical_tile == grids.get_physical_type(ix, iy)) {
io_sides.insert(NUM_SIDES);
center_io = true;
break;
@ -108,7 +108,8 @@ std::set<e_side> find_physical_io_tile_located_sides(
for (const e_side& fpga_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[fpga_side]) {
/* If located in center, we add a NUM_SIDES and finish */
if (physical_tile == grids[io_coordinate.x()][io_coordinate.y()].type) {
if (physical_tile ==
grids.get_physical_type(io_coordinate.x(), io_coordinate.y())) {
io_sides.insert(fpga_side);
break;
}

2
openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
View File

@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal ${OPENFPGA_VPR_DEVICE_LAYOUT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

4
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
View File

@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.7626540661
#0.4628907144
clk[0] <= !clk[0];
end
end
@ -109,7 +109,7 @@ initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#10.6771574
#6.480470181
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin

182
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -9,20 +9,19 @@
##################################################
# Create clock
##################################################
create_clock clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10}
create_clock clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10}
##################################################
# Create input and output delays for used I/Os
##################################################
set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[27]
set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[15]
set_output_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[12]
set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[11]
set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[14]
set_output_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[1]
##################################################
# Disable timing for unused I/Os
##################################################
set_disable_timing gfpga_pad_GPIO_PAD[0]
set_disable_timing gfpga_pad_GPIO_PAD[1]
set_disable_timing gfpga_pad_GPIO_PAD[2]
set_disable_timing gfpga_pad_GPIO_PAD[3]
set_disable_timing gfpga_pad_GPIO_PAD[4]
@ -32,9 +31,9 @@ set_disable_timing gfpga_pad_GPIO_PAD[7]
set_disable_timing gfpga_pad_GPIO_PAD[8]
set_disable_timing gfpga_pad_GPIO_PAD[9]
set_disable_timing gfpga_pad_GPIO_PAD[10]
set_disable_timing gfpga_pad_GPIO_PAD[11]
set_disable_timing gfpga_pad_GPIO_PAD[12]
set_disable_timing gfpga_pad_GPIO_PAD[13]
set_disable_timing gfpga_pad_GPIO_PAD[14]
set_disable_timing gfpga_pad_GPIO_PAD[15]
set_disable_timing gfpga_pad_GPIO_PAD[16]
set_disable_timing gfpga_pad_GPIO_PAD[17]
set_disable_timing gfpga_pad_GPIO_PAD[18]
@ -46,6 +45,7 @@ set_disable_timing gfpga_pad_GPIO_PAD[23]
set_disable_timing gfpga_pad_GPIO_PAD[24]
set_disable_timing gfpga_pad_GPIO_PAD[25]
set_disable_timing gfpga_pad_GPIO_PAD[26]
set_disable_timing gfpga_pad_GPIO_PAD[27]
set_disable_timing gfpga_pad_GPIO_PAD[28]
set_disable_timing gfpga_pad_GPIO_PAD[29]
set_disable_timing gfpga_pad_GPIO_PAD[30]
@ -156,9 +156,11 @@ set_disable_timing cbx_1__0_/chanx_left_in[7]
set_disable_timing cbx_1__0_/chanx_right_in[7]
set_disable_timing cbx_1__0_/chanx_left_in[8]
set_disable_timing cbx_1__0_/chanx_right_in[8]
set_disable_timing cbx_1__0_/chanx_left_in[9]
set_disable_timing cbx_1__0_/chanx_right_in[9]
set_disable_timing cbx_1__0_/chanx_left_in[10]
set_disable_timing cbx_1__0_/chanx_right_in[10]
set_disable_timing cbx_1__0_/chanx_left_in[11]
set_disable_timing cbx_1__0_/chanx_right_in[11]
set_disable_timing cbx_1__0_/chanx_left_in[12]
set_disable_timing cbx_1__0_/chanx_right_in[12]
@ -180,9 +182,11 @@ set_disable_timing cbx_1__0_/chanx_left_out[7]
set_disable_timing cbx_1__0_/chanx_right_out[7]
set_disable_timing cbx_1__0_/chanx_left_out[8]
set_disable_timing cbx_1__0_/chanx_right_out[8]
set_disable_timing cbx_1__0_/chanx_left_out[9]
set_disable_timing cbx_1__0_/chanx_right_out[9]
set_disable_timing cbx_1__0_/chanx_left_out[10]
set_disable_timing cbx_1__0_/chanx_right_out[10]
set_disable_timing cbx_1__0_/chanx_left_out[11]
set_disable_timing cbx_1__0_/chanx_right_out[11]
set_disable_timing cbx_1__0_/chanx_left_out[12]
set_disable_timing cbx_1__0_/chanx_right_out[12]
@ -272,6 +276,7 @@ set_disable_timing cbx_1__1_/chanx_left_in[1]
set_disable_timing cbx_1__1_/chanx_left_in[2]
set_disable_timing cbx_1__1_/chanx_right_in[2]
set_disable_timing cbx_1__1_/chanx_left_in[3]
set_disable_timing cbx_1__1_/chanx_right_in[3]
set_disable_timing cbx_1__1_/chanx_left_in[4]
set_disable_timing cbx_1__1_/chanx_right_in[4]
set_disable_timing cbx_1__1_/chanx_left_in[5]
@ -280,6 +285,7 @@ set_disable_timing cbx_1__1_/chanx_left_in[6]
set_disable_timing cbx_1__1_/chanx_right_in[6]
set_disable_timing cbx_1__1_/chanx_left_in[7]
set_disable_timing cbx_1__1_/chanx_right_in[7]
set_disable_timing cbx_1__1_/chanx_left_in[8]
set_disable_timing cbx_1__1_/chanx_right_in[8]
set_disable_timing cbx_1__1_/chanx_left_in[9]
set_disable_timing cbx_1__1_/chanx_right_in[9]
@ -295,6 +301,7 @@ set_disable_timing cbx_1__1_/chanx_left_out[1]
set_disable_timing cbx_1__1_/chanx_left_out[2]
set_disable_timing cbx_1__1_/chanx_right_out[2]
set_disable_timing cbx_1__1_/chanx_left_out[3]
set_disable_timing cbx_1__1_/chanx_right_out[3]
set_disable_timing cbx_1__1_/chanx_left_out[4]
set_disable_timing cbx_1__1_/chanx_right_out[4]
set_disable_timing cbx_1__1_/chanx_left_out[5]
@ -303,6 +310,7 @@ set_disable_timing cbx_1__1_/chanx_left_out[6]
set_disable_timing cbx_1__1_/chanx_right_out[6]
set_disable_timing cbx_1__1_/chanx_left_out[7]
set_disable_timing cbx_1__1_/chanx_right_out[7]
set_disable_timing cbx_1__1_/chanx_left_out[8]
set_disable_timing cbx_1__1_/chanx_right_out[8]
set_disable_timing cbx_1__1_/chanx_left_out[9]
set_disable_timing cbx_1__1_/chanx_right_out[9]
@ -313,13 +321,13 @@ set_disable_timing cbx_1__1_/chanx_right_out[11]
set_disable_timing cbx_1__1_/chanx_left_out[12]
set_disable_timing cbx_1__1_/chanx_right_out[12]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0]
set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1]
@ -331,7 +339,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0]
set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1]
set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3]
@ -367,6 +374,7 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[4]
set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[5]
set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4]
@ -396,6 +404,7 @@ set_disable_timing cby_0__1_/chany_bottom_in[1]
set_disable_timing cby_0__1_/chany_top_in[1]
set_disable_timing cby_0__1_/chany_bottom_in[2]
set_disable_timing cby_0__1_/chany_top_in[2]
set_disable_timing cby_0__1_/chany_bottom_in[3]
set_disable_timing cby_0__1_/chany_top_in[3]
set_disable_timing cby_0__1_/chany_bottom_in[4]
set_disable_timing cby_0__1_/chany_top_in[4]
@ -406,9 +415,11 @@ set_disable_timing cby_0__1_/chany_top_in[6]
set_disable_timing cby_0__1_/chany_bottom_in[7]
set_disable_timing cby_0__1_/chany_top_in[7]
set_disable_timing cby_0__1_/chany_bottom_in[8]
set_disable_timing cby_0__1_/chany_top_in[8]
set_disable_timing cby_0__1_/chany_bottom_in[9]
set_disable_timing cby_0__1_/chany_top_in[9]
set_disable_timing cby_0__1_/chany_bottom_in[10]
set_disable_timing cby_0__1_/chany_top_in[10]
set_disable_timing cby_0__1_/chany_bottom_in[11]
set_disable_timing cby_0__1_/chany_top_in[11]
set_disable_timing cby_0__1_/chany_bottom_in[12]
@ -419,6 +430,7 @@ set_disable_timing cby_0__1_/chany_bottom_out[1]
set_disable_timing cby_0__1_/chany_top_out[1]
set_disable_timing cby_0__1_/chany_bottom_out[2]
set_disable_timing cby_0__1_/chany_top_out[2]
set_disable_timing cby_0__1_/chany_bottom_out[3]
set_disable_timing cby_0__1_/chany_top_out[3]
set_disable_timing cby_0__1_/chany_bottom_out[4]
set_disable_timing cby_0__1_/chany_top_out[4]
@ -429,9 +441,11 @@ set_disable_timing cby_0__1_/chany_top_out[6]
set_disable_timing cby_0__1_/chany_bottom_out[7]
set_disable_timing cby_0__1_/chany_top_out[7]
set_disable_timing cby_0__1_/chany_bottom_out[8]
set_disable_timing cby_0__1_/chany_top_out[8]
set_disable_timing cby_0__1_/chany_bottom_out[9]
set_disable_timing cby_0__1_/chany_top_out[9]
set_disable_timing cby_0__1_/chany_bottom_out[10]
set_disable_timing cby_0__1_/chany_top_out[10]
set_disable_timing cby_0__1_/chany_bottom_out[11]
set_disable_timing cby_0__1_/chany_top_out[11]
set_disable_timing cby_0__1_/chany_bottom_out[12]
@ -510,44 +524,46 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
# Disable timing for Connection block cby_1__1_
##################################################
set_disable_timing cby_1__1_/chany_top_in[0]
set_disable_timing cby_1__1_/chany_bottom_in[1]
set_disable_timing cby_1__1_/chany_top_in[1]
set_disable_timing cby_1__1_/chany_bottom_in[2]
set_disable_timing cby_1__1_/chany_top_in[2]
set_disable_timing cby_1__1_/chany_bottom_in[3]
set_disable_timing cby_1__1_/chany_top_in[3]
set_disable_timing cby_1__1_/chany_bottom_in[4]
set_disable_timing cby_1__1_/chany_top_in[4]
set_disable_timing cby_1__1_/chany_bottom_in[5]
set_disable_timing cby_1__1_/chany_top_in[5]
set_disable_timing cby_1__1_/chany_bottom_in[6]
set_disable_timing cby_1__1_/chany_top_in[6]
set_disable_timing cby_1__1_/chany_bottom_in[7]
set_disable_timing cby_1__1_/chany_top_in[7]
set_disable_timing cby_1__1_/chany_bottom_in[8]
set_disable_timing cby_1__1_/chany_top_in[8]
set_disable_timing cby_1__1_/chany_bottom_in[9]
set_disable_timing cby_1__1_/chany_top_in[9]
set_disable_timing cby_1__1_/chany_bottom_in[10]
set_disable_timing cby_1__1_/chany_top_in[10]
set_disable_timing cby_1__1_/chany_bottom_in[11]
set_disable_timing cby_1__1_/chany_top_in[11]
set_disable_timing cby_1__1_/chany_bottom_in[12]
set_disable_timing cby_1__1_/chany_top_in[12]
set_disable_timing cby_1__1_/chany_top_out[0]
set_disable_timing cby_1__1_/chany_bottom_out[1]
set_disable_timing cby_1__1_/chany_top_out[1]
set_disable_timing cby_1__1_/chany_bottom_out[2]
set_disable_timing cby_1__1_/chany_top_out[2]
set_disable_timing cby_1__1_/chany_bottom_out[3]
set_disable_timing cby_1__1_/chany_top_out[3]
set_disable_timing cby_1__1_/chany_bottom_out[4]
set_disable_timing cby_1__1_/chany_top_out[4]
set_disable_timing cby_1__1_/chany_bottom_out[5]
set_disable_timing cby_1__1_/chany_top_out[5]
set_disable_timing cby_1__1_/chany_bottom_out[6]
set_disable_timing cby_1__1_/chany_top_out[6]
set_disable_timing cby_1__1_/chany_bottom_out[7]
set_disable_timing cby_1__1_/chany_top_out[7]
set_disable_timing cby_1__1_/chany_bottom_out[8]
set_disable_timing cby_1__1_/chany_top_out[8]
set_disable_timing cby_1__1_/chany_bottom_out[9]
set_disable_timing cby_1__1_/chany_top_out[9]
set_disable_timing cby_1__1_/chany_bottom_out[10]
set_disable_timing cby_1__1_/chany_top_out[10]
set_disable_timing cby_1__1_/chany_bottom_out[11]
set_disable_timing cby_1__1_/chany_top_out[11]
@ -557,11 +573,11 @@ set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_out
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0]
set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0]
set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0]
set_disable_timing cby_1__1_/mux_left_ipin_0/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_7/in[1]
@ -570,6 +586,7 @@ set_disable_timing cby_1__1_/mux_left_ipin_1/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_7/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[1]
set_disable_timing cby_1__1_/mux_right_ipin_0/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[0]
set_disable_timing cby_1__1_/mux_right_ipin_0/in[0]
@ -585,6 +602,7 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_3/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[0]
set_disable_timing cby_1__1_/mux_right_ipin_2/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_5/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_5/in[0]
@ -600,7 +618,6 @@ set_disable_timing cby_1__1_/mux_left_ipin_6/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_7/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[5]
set_disable_timing cby_1__1_/mux_left_ipin_7/in[5]
set_disable_timing cby_1__1_/mux_right_ipin_0/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[4]
set_disable_timing cby_1__1_/mux_left_ipin_7/in[4]
set_disable_timing cby_1__1_/mux_right_ipin_0/in[2]
@ -617,7 +634,6 @@ set_disable_timing cby_1__1_/mux_left_ipin_3/in[4]
set_disable_timing cby_1__1_/mux_right_ipin_1/in[4]
set_disable_timing cby_1__1_/mux_right_ipin_2/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[5]
set_disable_timing cby_1__1_/mux_right_ipin_2/in[5]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[4]
set_disable_timing cby_1__1_/mux_right_ipin_2/in[4]
set_disable_timing cby_1__1_/mux_left_ipin_5/in[5]
@ -635,6 +651,7 @@ set_disable_timing sb_0__0_/chany_top_out[1]
set_disable_timing sb_0__0_/chany_top_in[1]
set_disable_timing sb_0__0_/chany_top_out[2]
set_disable_timing sb_0__0_/chany_top_in[2]
set_disable_timing sb_0__0_/chany_top_out[3]
set_disable_timing sb_0__0_/chany_top_in[3]
set_disable_timing sb_0__0_/chany_top_out[4]
set_disable_timing sb_0__0_/chany_top_in[4]
@ -645,9 +662,11 @@ set_disable_timing sb_0__0_/chany_top_in[6]
set_disable_timing sb_0__0_/chany_top_out[7]
set_disable_timing sb_0__0_/chany_top_in[7]
set_disable_timing sb_0__0_/chany_top_out[8]
set_disable_timing sb_0__0_/chany_top_in[8]
set_disable_timing sb_0__0_/chany_top_out[9]
set_disable_timing sb_0__0_/chany_top_in[9]
set_disable_timing sb_0__0_/chany_top_out[10]
set_disable_timing sb_0__0_/chany_top_in[10]
set_disable_timing sb_0__0_/chany_top_out[11]
set_disable_timing sb_0__0_/chany_top_in[11]
set_disable_timing sb_0__0_/chany_top_out[12]
@ -670,15 +689,18 @@ set_disable_timing sb_0__0_/chanx_right_out[7]
set_disable_timing sb_0__0_/chanx_right_in[7]
set_disable_timing sb_0__0_/chanx_right_out[8]
set_disable_timing sb_0__0_/chanx_right_in[8]
set_disable_timing sb_0__0_/chanx_right_out[9]
set_disable_timing sb_0__0_/chanx_right_in[9]
set_disable_timing sb_0__0_/chanx_right_out[10]
set_disable_timing sb_0__0_/chanx_right_in[10]
set_disable_timing sb_0__0_/chanx_right_out[11]
set_disable_timing sb_0__0_/chanx_right_in[11]
set_disable_timing sb_0__0_/chanx_right_out[12]
set_disable_timing sb_0__0_/chanx_right_in[12]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
@ -703,6 +725,7 @@ set_disable_timing sb_0__0_/mux_top_track_2/in[1]
set_disable_timing sb_0__0_/mux_top_track_4/in[0]
set_disable_timing sb_0__0_/mux_top_track_16/in[0]
set_disable_timing sb_0__0_/mux_top_track_4/in[1]
set_disable_timing sb_0__0_/mux_top_track_6/in[0]
set_disable_timing sb_0__0_/mux_top_track_18/in[0]
set_disable_timing sb_0__0_/mux_top_track_6/in[1]
set_disable_timing sb_0__0_/mux_top_track_8/in[0]
@ -752,7 +775,9 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0]
set_disable_timing sb_0__0_/mux_right_track_12/in[0]
set_disable_timing sb_0__0_/mux_right_track_14/in[0]
set_disable_timing sb_0__0_/mux_right_track_16/in[0]
set_disable_timing sb_0__0_/mux_right_track_18/in[0]
set_disable_timing sb_0__0_/mux_right_track_20/in[0]
set_disable_timing sb_0__0_/mux_right_track_22/in[0]
set_disable_timing sb_0__0_/mux_right_track_24/in[0]
set_disable_timing sb_0__0_/mux_right_track_0/in[0]
set_disable_timing sb_0__0_/mux_top_track_24/in[2]
@ -777,6 +802,7 @@ set_disable_timing sb_0__1_/chanx_right_out[1]
set_disable_timing sb_0__1_/chanx_right_out[2]
set_disable_timing sb_0__1_/chanx_right_in[2]
set_disable_timing sb_0__1_/chanx_right_out[3]
set_disable_timing sb_0__1_/chanx_right_in[3]
set_disable_timing sb_0__1_/chanx_right_out[4]
set_disable_timing sb_0__1_/chanx_right_in[4]
set_disable_timing sb_0__1_/chanx_right_out[5]
@ -785,6 +811,7 @@ set_disable_timing sb_0__1_/chanx_right_out[6]
set_disable_timing sb_0__1_/chanx_right_in[6]
set_disable_timing sb_0__1_/chanx_right_out[7]
set_disable_timing sb_0__1_/chanx_right_in[7]
set_disable_timing sb_0__1_/chanx_right_out[8]
set_disable_timing sb_0__1_/chanx_right_in[8]
set_disable_timing sb_0__1_/chanx_right_out[9]
set_disable_timing sb_0__1_/chanx_right_in[9]
@ -800,6 +827,7 @@ set_disable_timing sb_0__1_/chany_bottom_in[1]
set_disable_timing sb_0__1_/chany_bottom_out[1]
set_disable_timing sb_0__1_/chany_bottom_in[2]
set_disable_timing sb_0__1_/chany_bottom_out[2]
set_disable_timing sb_0__1_/chany_bottom_in[3]
set_disable_timing sb_0__1_/chany_bottom_out[3]
set_disable_timing sb_0__1_/chany_bottom_in[4]
set_disable_timing sb_0__1_/chany_bottom_out[4]
@ -810,9 +838,11 @@ set_disable_timing sb_0__1_/chany_bottom_out[6]
set_disable_timing sb_0__1_/chany_bottom_in[7]
set_disable_timing sb_0__1_/chany_bottom_out[7]
set_disable_timing sb_0__1_/chany_bottom_in[8]
set_disable_timing sb_0__1_/chany_bottom_out[8]
set_disable_timing sb_0__1_/chany_bottom_in[9]
set_disable_timing sb_0__1_/chany_bottom_out[9]
set_disable_timing sb_0__1_/chany_bottom_in[10]
set_disable_timing sb_0__1_/chany_bottom_out[10]
set_disable_timing sb_0__1_/chany_bottom_in[11]
set_disable_timing sb_0__1_/chany_bottom_out[11]
set_disable_timing sb_0__1_/chany_bottom_in[12]
@ -830,6 +860,7 @@ set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__p
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
@ -885,7 +916,9 @@ set_disable_timing sb_0__1_/mux_bottom_track_3/in[3]
set_disable_timing sb_0__1_/mux_bottom_track_15/in[3]
set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
set_disable_timing sb_0__1_/mux_bottom_track_23/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_21/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_19/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_17/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_15/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_13/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_11/in[0]
@ -898,6 +931,7 @@ set_disable_timing sb_0__1_/mux_bottom_track_25/in[0]
set_disable_timing sb_0__1_/mux_right_track_22/in[1]
set_disable_timing sb_0__1_/mux_right_track_20/in[1]
set_disable_timing sb_0__1_/mux_right_track_18/in[1]
set_disable_timing sb_0__1_/mux_right_track_16/in[2]
set_disable_timing sb_0__1_/mux_right_track_14/in[2]
set_disable_timing sb_0__1_/mux_right_track_12/in[3]
set_disable_timing sb_0__1_/mux_right_track_10/in[2]
@ -911,22 +945,23 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2]
# Disable timing for Switch block sb_1__0_
##################################################
set_disable_timing sb_1__0_/chany_top_in[0]
set_disable_timing sb_1__0_/chany_top_out[1]
set_disable_timing sb_1__0_/chany_top_in[1]
set_disable_timing sb_1__0_/chany_top_out[2]
set_disable_timing sb_1__0_/chany_top_in[2]
set_disable_timing sb_1__0_/chany_top_out[3]
set_disable_timing sb_1__0_/chany_top_in[3]
set_disable_timing sb_1__0_/chany_top_out[4]
set_disable_timing sb_1__0_/chany_top_in[4]
set_disable_timing sb_1__0_/chany_top_out[5]
set_disable_timing sb_1__0_/chany_top_in[5]
set_disable_timing sb_1__0_/chany_top_out[6]
set_disable_timing sb_1__0_/chany_top_in[6]
set_disable_timing sb_1__0_/chany_top_out[7]
set_disable_timing sb_1__0_/chany_top_in[7]
set_disable_timing sb_1__0_/chany_top_out[8]
set_disable_timing sb_1__0_/chany_top_in[8]
set_disable_timing sb_1__0_/chany_top_out[9]
set_disable_timing sb_1__0_/chany_top_in[9]
set_disable_timing sb_1__0_/chany_top_out[10]
set_disable_timing sb_1__0_/chany_top_in[10]
set_disable_timing sb_1__0_/chany_top_out[11]
set_disable_timing sb_1__0_/chany_top_in[11]
@ -950,19 +985,20 @@ set_disable_timing sb_1__0_/chanx_left_in[7]
set_disable_timing sb_1__0_/chanx_left_out[7]
set_disable_timing sb_1__0_/chanx_left_in[8]
set_disable_timing sb_1__0_/chanx_left_out[8]
set_disable_timing sb_1__0_/chanx_left_in[9]
set_disable_timing sb_1__0_/chanx_left_out[9]
set_disable_timing sb_1__0_/chanx_left_in[10]
set_disable_timing sb_1__0_/chanx_left_out[10]
set_disable_timing sb_1__0_/chanx_left_in[11]
set_disable_timing sb_1__0_/chanx_left_out[11]
set_disable_timing sb_1__0_/chanx_left_in[12]
set_disable_timing sb_1__0_/chanx_left_out[12]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0]
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0]
@ -983,7 +1019,6 @@ set_disable_timing sb_1__0_/mux_top_track_6/in[0]
set_disable_timing sb_1__0_/mux_top_track_18/in[0]
set_disable_timing sb_1__0_/mux_top_track_6/in[1]
set_disable_timing sb_1__0_/mux_top_track_8/in[0]
set_disable_timing sb_1__0_/mux_top_track_20/in[0]
set_disable_timing sb_1__0_/mux_top_track_8/in[1]
set_disable_timing sb_1__0_/mux_top_track_10/in[0]
set_disable_timing sb_1__0_/mux_top_track_22/in[0]
@ -992,7 +1027,7 @@ set_disable_timing sb_1__0_/mux_top_track_12/in[0]
set_disable_timing sb_1__0_/mux_top_track_24/in[0]
set_disable_timing sb_1__0_/mux_top_track_0/in[2]
set_disable_timing sb_1__0_/mux_top_track_12/in[1]
set_disable_timing sb_1__0_/mux_top_track_14/in[1]
set_disable_timing sb_1__0_/mux_top_track_2/in[2]
set_disable_timing sb_1__0_/mux_top_track_14/in[2]
set_disable_timing sb_1__0_/mux_top_track_16/in[1]
set_disable_timing sb_1__0_/mux_left_track_1/in[1]
@ -1044,28 +1079,31 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2]
set_disable_timing sb_1__0_/mux_top_track_14/in[3]
set_disable_timing sb_1__0_/mux_top_track_12/in[2]
set_disable_timing sb_1__0_/mux_top_track_10/in[2]
set_disable_timing sb_1__0_/mux_top_track_8/in[2]
set_disable_timing sb_1__0_/mux_top_track_6/in[2]
set_disable_timing sb_1__0_/mux_top_track_4/in[2]
set_disable_timing sb_1__0_/mux_top_track_2/in[3]
##################################################
# Disable timing for Switch block sb_1__1_
##################################################
set_disable_timing sb_1__1_/chany_bottom_out[0]
set_disable_timing sb_1__1_/chany_bottom_in[1]
set_disable_timing sb_1__1_/chany_bottom_out[1]
set_disable_timing sb_1__1_/chany_bottom_in[2]
set_disable_timing sb_1__1_/chany_bottom_out[2]
set_disable_timing sb_1__1_/chany_bottom_in[3]
set_disable_timing sb_1__1_/chany_bottom_out[3]
set_disable_timing sb_1__1_/chany_bottom_in[4]
set_disable_timing sb_1__1_/chany_bottom_out[4]
set_disable_timing sb_1__1_/chany_bottom_in[5]
set_disable_timing sb_1__1_/chany_bottom_out[5]
set_disable_timing sb_1__1_/chany_bottom_in[6]
set_disable_timing sb_1__1_/chany_bottom_out[6]
set_disable_timing sb_1__1_/chany_bottom_in[7]
set_disable_timing sb_1__1_/chany_bottom_out[7]
set_disable_timing sb_1__1_/chany_bottom_in[8]
set_disable_timing sb_1__1_/chany_bottom_out[8]
set_disable_timing sb_1__1_/chany_bottom_in[9]
set_disable_timing sb_1__1_/chany_bottom_out[9]
set_disable_timing sb_1__1_/chany_bottom_in[10]
set_disable_timing sb_1__1_/chany_bottom_out[10]
set_disable_timing sb_1__1_/chany_bottom_in[11]
set_disable_timing sb_1__1_/chany_bottom_out[11]
@ -1077,6 +1115,7 @@ set_disable_timing sb_1__1_/chanx_left_in[1]
set_disable_timing sb_1__1_/chanx_left_in[2]
set_disable_timing sb_1__1_/chanx_left_out[2]
set_disable_timing sb_1__1_/chanx_left_in[3]
set_disable_timing sb_1__1_/chanx_left_out[3]
set_disable_timing sb_1__1_/chanx_left_in[4]
set_disable_timing sb_1__1_/chanx_left_out[4]
set_disable_timing sb_1__1_/chanx_left_in[5]
@ -1085,6 +1124,7 @@ set_disable_timing sb_1__1_/chanx_left_in[6]
set_disable_timing sb_1__1_/chanx_left_out[6]
set_disable_timing sb_1__1_/chanx_left_in[7]
set_disable_timing sb_1__1_/chanx_left_out[7]
set_disable_timing sb_1__1_/chanx_left_in[8]
set_disable_timing sb_1__1_/chanx_left_out[8]
set_disable_timing sb_1__1_/chanx_left_in[9]
set_disable_timing sb_1__1_/chanx_left_out[9]
@ -1097,10 +1137,9 @@ set_disable_timing sb_1__1_/chanx_left_out[12]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
@ -1161,6 +1200,7 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3]
set_disable_timing sb_1__1_/mux_left_track_15/in[2]
set_disable_timing sb_1__1_/mux_left_track_17/in[2]
set_disable_timing sb_1__1_/mux_left_track_5/in[0]
set_disable_timing sb_1__1_/mux_left_track_7/in[0]
set_disable_timing sb_1__1_/mux_left_track_9/in[0]
set_disable_timing sb_1__1_/mux_left_track_11/in[0]
set_disable_timing sb_1__1_/mux_left_track_13/in[0]
@ -1193,6 +1233,7 @@ set_disable_timing sb_1__1_/mux_bottom_track_23/in[1]
#######################################
# Disable unused pins for pb_graph_node clb[0]
#######################################
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[3]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4]
@ -1200,7 +1241,6 @@ set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[9]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[1]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[2]
@ -1426,16 +1466,20 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/*
#######################################
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[1][2][1]
# Disable Timing for unused resources in grid[1][2][1]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/*
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_inpad[0]
#######################################
# Disable all the ports for pb_graph_node iopad[0]
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_0_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
#######################################
# Disable Timing for unused grid[1][2][2]
#######################################
@ -1539,31 +1583,31 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/*
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[2][1][3]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/*
#######################################
# Disable all the ports for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused resources in grid[2][1][4]
# Disable Timing for unused resources in grid[2][1][3]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0]
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_outpad[0]
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0]
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused grid[2][1][4]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/*
#######################################
# Disable all the ports for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[2][1][5]
#######################################
@ -1576,31 +1620,31 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__5/*
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[2][1][6]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/*
#######################################
# Disable all the ports for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused resources in grid[2][1][7]
# Disable Timing for unused resources in grid[2][1][6]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/io_outpad[0]
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/io_outpad[0]
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7//direct_interc_1_/in[0]
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6//direct_interc_1_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused grid[2][1][7]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/*
#######################################
# Disable all the ports for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for grid[1][0]
#######################################
@ -1729,20 +1773,16 @@ set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/*
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused resources in grid[0][1][3]
# Disable Timing for unused grid[0][1][3]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
# Disable all the ports for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/io_outpad[0]
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/*
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
# Disable all the ports for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[0][1][4]
#######################################

98
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v
View File

@ -42,18 +42,17 @@ wire [0:0] clk_fm;
// ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[27] -----
assign gfpga_pad_GPIO_PAD_fm[27] = a[0];
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] -----
assign gfpga_pad_GPIO_PAD_fm[11] = a[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[15] -----
assign gfpga_pad_GPIO_PAD_fm[15] = b[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] -----
assign gfpga_pad_GPIO_PAD_fm[14] = b[0];
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
assign c[0] = gfpga_pad_GPIO_PAD_fm[12];
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] -----
assign c[0] = gfpga_pad_GPIO_PAD_fm[1];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0;
@ -63,9 +62,9 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
@ -77,6 +76,7 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0;
@ -125,8 +125,8 @@ initial begin
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0110;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1001;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
@ -135,8 +135,8 @@ initial begin
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@ -157,8 +157,8 @@ initial begin
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@ -203,8 +203,8 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
@ -241,12 +241,12 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
@ -265,8 +265,8 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
@ -291,38 +291,38 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = 3'b001;
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = 3'b110;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:2] = 3'b011;
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:2] = 3'b100;
force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}};
@ -385,8 +385,8 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@ -429,8 +429,8 @@ initial begin
force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001;
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110;
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
@ -443,8 +443,8 @@ initial begin
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = 3'b110;
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = 3'b001;
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
@ -477,20 +477,20 @@ initial begin
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101;
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010;
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = 3'b101;
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = 3'b010;
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = 3'b110;
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:2] = 3'b001;
end
// ----- End assign bitstream to configuration memories -----
// ----- End load bitstream to configuration memories -----

54
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -13,10 +13,10 @@
0
0
0
0
1
1
1
1
0
0
0
0
@ -138,13 +138,13 @@
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
@ -155,9 +155,7 @@
0
0
0
1
0
1
0
0
0
@ -239,10 +237,15 @@
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
@ -251,12 +254,9 @@
0
0
0
1
0
0
0
1
1
0
0
1
@ -302,12 +302,8 @@
0
0
0
1
1
0
0
1
1
0
0
0
@ -349,8 +345,6 @@
0
0
0
1
1
0
0
0
@ -362,12 +356,8 @@
0
0
0
1
1
0
0
1
1
0
0
0
@ -396,7 +386,17 @@
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -421,7 +421,7 @@
1
1
1
1
0
1
0
0
@ -430,8 +430,6 @@
0
0
0
1
1
0
0
0
@ -452,6 +450,10 @@
0
0
0
1
0
0
0
0
0
0
@ -475,8 +477,6 @@
0
0
0
1
1
0
0
1
@ -515,7 +515,7 @@
1
1
1
0
1
1
1
1

64
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
View File

@ -30,13 +30,13 @@
</bit>
<bit id="515" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
</bit>
<bit id="514" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
<bit id="514" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
</bit>
<bit id="513" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
</bit>
<bit id="512" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
</bit>
<bit id="511" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
<bit id="511" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
</bit>
<bit id="510" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
</bit>
@ -280,9 +280,9 @@
</bit>
<bit id="390" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_2.mem_out[2]">
</bit>
<bit id="389" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_2.mem_out[1]">
<bit id="389" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_2.mem_out[1]">
</bit>
<bit id="388" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_2.mem_out[0]">
<bit id="388" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_2.mem_out[0]">
</bit>
<bit id="387" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_1.mem_out[2]">
</bit>
@ -292,7 +292,7 @@
</bit>
<bit id="384" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[2]">
</bit>
<bit id="383" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[1]">
<bit id="383" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[1]">
</bit>
<bit id="382" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[0]">
</bit>
@ -314,11 +314,11 @@
</bit>
<bit id="373" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_5.mem_out[0]">
</bit>
<bit id="372" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
<bit id="372" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
</bit>
<bit id="371" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[1]">
</bit>
<bit id="370" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
<bit id="370" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
</bit>
<bit id="369" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
</bit>
@ -478,9 +478,9 @@
</bit>
<bit id="291" value="0" path="fpga_top.sb_1__0_.mem_top_track_22.mem_out[0]">
</bit>
<bit id="290" value="0" path="fpga_top.sb_1__0_.mem_top_track_20.mem_out[1]">
<bit id="290" value="1" path="fpga_top.sb_1__0_.mem_top_track_20.mem_out[1]">
</bit>
<bit id="289" value="0" path="fpga_top.sb_1__0_.mem_top_track_20.mem_out[0]">
<bit id="289" value="1" path="fpga_top.sb_1__0_.mem_top_track_20.mem_out[0]">
</bit>
<bit id="288" value="0" path="fpga_top.sb_1__0_.mem_top_track_18.mem_out[1]">
</bit>
@ -490,9 +490,9 @@
</bit>
<bit id="285" value="0" path="fpga_top.sb_1__0_.mem_top_track_16.mem_out[0]">
</bit>
<bit id="284" value="0" path="fpga_top.sb_1__0_.mem_top_track_14.mem_out[2]">
<bit id="284" value="1" path="fpga_top.sb_1__0_.mem_top_track_14.mem_out[2]">
</bit>
<bit id="283" value="0" path="fpga_top.sb_1__0_.mem_top_track_14.mem_out[1]">
<bit id="283" value="1" path="fpga_top.sb_1__0_.mem_top_track_14.mem_out[1]">
</bit>
<bit id="282" value="0" path="fpga_top.sb_1__0_.mem_top_track_14.mem_out[0]">
</bit>
@ -506,7 +506,7 @@
</bit>
<bit id="277" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[1]">
</bit>
<bit id="276" value="1" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
<bit id="276" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
</bit>
<bit id="275" value="0" path="fpga_top.sb_1__0_.mem_top_track_6.mem_out[1]">
</bit>
@ -514,9 +514,9 @@
</bit>
<bit id="273" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[1]">
</bit>
<bit id="272" value="1" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
<bit id="272" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
</bit>
<bit id="271" value="1" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
<bit id="271" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
</bit>
<bit id="270" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[1]">
</bit>
@ -608,17 +608,17 @@
</bit>
<bit id="226" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[0]">
</bit>
<bit id="225" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
<bit id="225" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
</bit>
<bit id="224" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
<bit id="224" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
</bit>
<bit id="223" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[1]">
</bit>
<bit id="222" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[0]">
</bit>
<bit id="221" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
<bit id="221" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
</bit>
<bit id="220" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
<bit id="220" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
</bit>
<bit id="219" value="0" path="fpga_top.sb_0__0_.mem_right_track_16.mem_out[1]">
</bit>
@ -702,9 +702,9 @@
</bit>
<bit id="179" value="0" path="fpga_top.sb_0__0_.mem_top_track_8.mem_out[0]">
</bit>
<bit id="178" value="1" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[1]">
<bit id="178" value="0" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[1]">
</bit>
<bit id="177" value="1" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[0]">
<bit id="177" value="0" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[0]">
</bit>
<bit id="176" value="0" path="fpga_top.sb_0__0_.mem_top_track_4.mem_out[1]">
</bit>
@ -728,17 +728,17 @@
</bit>
<bit id="166" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_23.mem_out[0]">
</bit>
<bit id="165" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
<bit id="165" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
</bit>
<bit id="164" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
<bit id="164" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
</bit>
<bit id="163" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[1]">
</bit>
<bit id="162" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[0]">
</bit>
<bit id="161" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
<bit id="161" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
</bit>
<bit id="160" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
<bit id="160" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
</bit>
<bit id="159" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_15.mem_out[2]">
</bit>
@ -796,7 +796,7 @@
</bit>
<bit id="132" value="0" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[1]">
</bit>
<bit id="131" value="1" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[0]">
<bit id="131" value="0" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[0]">
</bit>
<bit id="130" value="0" path="fpga_top.sb_0__1_.mem_right_track_14.mem_out[1]">
</bit>
@ -846,7 +846,7 @@
</bit>
<bit id="107" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="106" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
<bit id="106" value="0" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="105" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
@ -864,9 +864,9 @@
</bit>
<bit id="98" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[2]">
</bit>
<bit id="97" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[1]">
<bit id="97" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[1]">
</bit>
<bit id="96" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]">
<bit id="96" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]">
</bit>
<bit id="95" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_7.mem_out[2]">
</bit>
@ -904,7 +904,7 @@
</bit>
<bit id="78" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_2.mem_out[0]">
</bit>
<bit id="77" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
<bit id="77" value="1" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
</bit>
<bit id="76" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[1]">
</bit>
@ -954,9 +954,9 @@
</bit>
<bit id="53" value="0" path="fpga_top.sb_1__1_.mem_left_track_9.mem_out[0]">
</bit>
<bit id="52" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
<bit id="52" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
</bit>
<bit id="51" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
<bit id="51" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
</bit>
<bit id="50" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[1]">
</bit>
@ -1034,7 +1034,7 @@
</bit>
<bit id="13" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="12" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
<bit id="12" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="11" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>

270
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
View File

@ -431,7 +431,7 @@
<instance level="3" name="mem_fle_3_in_0"/>
</hierarchy>
<input_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
@ -440,7 +440,7 @@
<path id="6" net_name="unmapped"/>
<path id="7" net_name="unmapped"/>
<path id="8" net_name="unmapped"/>
<path id="9" net_name="unmapped"/>
<path id="9" net_name="a"/>
<path id="10" net_name="unmapped"/>
<path id="11" net_name="unmapped"/>
<path id="12" net_name="unmapped"/>
@ -449,11 +449,11 @@
<output_nets>
<path id="0" net_name="a"/>
</output_nets>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bitstream path_id="9">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[2]" value="1"/>
<bit memory_port="mem_out[3]" value="1"/>
<bit memory_port="mem_out[3]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_fle_3_in_1" hierarchy_level="3">
@ -498,7 +498,7 @@
<instance level="3" name="mem_fle_3_in_3"/>
</hierarchy>
<input_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
@ -507,7 +507,7 @@
<path id="6" net_name="unmapped"/>
<path id="7" net_name="unmapped"/>
<path id="8" net_name="unmapped"/>
<path id="9" net_name="unmapped"/>
<path id="9" net_name="a"/>
<path id="10" net_name="unmapped"/>
<path id="11" net_name="unmapped"/>
<path id="12" net_name="unmapped"/>
@ -553,7 +553,7 @@
<instance level="4" name="GPIO_DFF_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[0]" value="0"/>
</bitstream>
</bitstream_block>
</bitstream_block>
@ -731,7 +731,7 @@
<instance level="4" name="GPIO_DFF_mem"/>
</hierarchy>
<bitstream>
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[0]" value="1"/>
</bitstream>
</bitstream_block>
</bitstream_block>
@ -1094,7 +1094,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="a"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -1112,16 +1112,16 @@
<instance level="2" name="mem_top_track_6"/>
</hierarchy>
<input_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_top_track_8" hierarchy_level="2">
@ -1228,7 +1228,7 @@
<instance level="2" name="mem_top_track_18"/>
</hierarchy>
<input_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -1480,15 +1480,15 @@
<instance level="2" name="mem_right_track_18"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_right_track_20" hierarchy_level="2">
@ -1516,15 +1516,15 @@
<instance level="2" name="mem_right_track_22"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_right_track_24" hierarchy_level="2">
@ -1713,13 +1713,13 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="a"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="2">
<bit memory_port="mem_out[0]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
@ -1866,7 +1866,7 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="a"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
@ -1884,7 +1884,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="a"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -1961,16 +1961,16 @@
<instance level="2" name="mem_bottom_track_17"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_bottom_track_19" hierarchy_level="2">
@ -1999,14 +1999,14 @@
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="1" net_name="a"/>
<path id="1" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_bottom_track_23" hierarchy_level="2">
@ -2056,7 +2056,7 @@
<input_nets>
<path id="0" net_name="c"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="2" net_name="b"/>
<path id="3" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2077,16 +2077,16 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="b"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="b"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="2">
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/>
<bit memory_port="mem_out[2]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_top_track_4" hierarchy_level="2">
@ -2098,13 +2098,13 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="c"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="2">
<bit memory_port="mem_out[0]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
@ -2116,7 +2116,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="1" net_name="a"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2134,15 +2134,15 @@
<instance level="2" name="mem_top_track_8"/>
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="c"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="2">
<bit memory_port="mem_out[0]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
@ -2173,7 +2173,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2192,17 +2192,17 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="b"/>
<path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="b"/>
</output_nets>
<bitstream path_id="-1">
<bitstream path_id="1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="0"/>
<bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[2]" value="1"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_top_track_16" hierarchy_level="2">
@ -2213,7 +2213,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="b"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2249,15 +2249,15 @@
<instance level="2" name="mem_top_track_20"/>
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="a"/>
</output_nets>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_top_track_22" hierarchy_level="2">
@ -2559,7 +2559,7 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="b"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2598,7 +2598,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="1" net_name="a"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2616,7 +2616,7 @@
<instance level="2" name="mem_bottom_track_7"/>
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
@ -2655,7 +2655,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2674,8 +2674,8 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="b"/>
<path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2695,8 +2695,8 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="b"/>
<path id="2" net_name="a"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
@ -2732,7 +2732,7 @@
<instance level="2" name="mem_bottom_track_19"/>
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2787,7 +2787,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -2845,7 +2845,7 @@
<instance level="2" name="mem_left_track_5"/>
</hierarchy>
<input_nets>
<path id="0" net_name="b"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
@ -2864,16 +2864,16 @@
<instance level="2" name="mem_left_track_7"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="0">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_left_track_9" hierarchy_level="2">
@ -2902,7 +2902,7 @@
<instance level="2" name="mem_left_track_11"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
@ -2961,7 +2961,7 @@
<instance level="2" name="mem_left_track_17"/>
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="b"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
</input_nets>
@ -3016,7 +3016,7 @@
<instance level="2" name="mem_left_track_23"/>
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -3128,7 +3128,7 @@
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="c"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -3174,7 +3174,7 @@
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="c"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -3266,7 +3266,7 @@
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="c"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -3287,7 +3287,7 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="c"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
@ -3341,12 +3341,12 @@
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="c"/>
</output_nets>
<bitstream path_id="-1">
<bitstream path_id="3">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_bottom_ipin_2" hierarchy_level="2">
@ -3360,7 +3360,7 @@
<path id="1" net_name="c"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="a"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -3382,7 +3382,7 @@
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="c"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
</input_nets>
@ -3403,7 +3403,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="c"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
@ -3498,15 +3498,15 @@
<path id="1" net_name="c"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="a"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="4">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="0"/>
</bitstream>
</bitstream_block>
@ -3519,7 +3519,7 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="a"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
@ -3541,7 +3541,7 @@
</hierarchy>
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="c"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
@ -3616,7 +3616,7 @@
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="c"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
@ -3636,7 +3636,7 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="a"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
@ -3657,12 +3657,12 @@
<instance level="2" name="mem_right_ipin_2"/>
</hierarchy>
<input_nets>
<path id="0" net_name="a"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="c"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
@ -3754,7 +3754,7 @@
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="c"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
@ -3775,7 +3775,7 @@
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="c"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
</input_nets>
@ -3822,9 +3822,9 @@
<input_nets>
<path id="0" net_name="c"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="b"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="4" net_name="b"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -3843,9 +3843,9 @@
<instance level="2" name="mem_left_ipin_2"/>
</hierarchy>
<input_nets>
<path id="0" net_name="b"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="c"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
@ -3866,7 +3866,7 @@
<instance level="2" name="mem_left_ipin_3"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
@ -3891,18 +3891,18 @@
<input_nets>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="c"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="4" net_name="a"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
</output_nets>
<bitstream path_id="2">
<bit memory_port="mem_out[0]" value="1"/>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/>
<bit memory_port="mem_out[2]" value="0"/>
</bitstream>
</bitstream_block>
<bitstream_block name="mem_left_ipin_5" hierarchy_level="2">
@ -3912,7 +3912,7 @@
<instance level="2" name="mem_left_ipin_5"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
@ -3962,7 +3962,7 @@
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="4" net_name="b"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
@ -3981,9 +3981,9 @@
<instance level="2" name="mem_right_ipin_0"/>
</hierarchy>
<input_nets>
<path id="0" net_name="b"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="2" net_name="b"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/>
@ -3991,9 +3991,9 @@
<output_nets>
<path id="0" net_name="b"/>
</output_nets>
<bitstream path_id="0">
<bitstream path_id="2">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/>
</bitstream>
</bitstream_block>
@ -4004,7 +4004,7 @@
<instance level="2" name="mem_right_ipin_1"/>
</hierarchy>
<input_nets>
<path id="0" net_name="c"/>
<path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
@ -4031,15 +4031,15 @@
<path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/>
<path id="4" net_name="a"/>
<path id="5" net_name="unmapped"/>
</input_nets>
<output_nets>
<path id="0" net_name="unmapped"/>
<path id="0" net_name="a"/>
</output_nets>
<bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/>
<bitstream path_id="4">
<bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[2]" value="0"/>
</bitstream>
</bitstream_block>

2
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc
View File

@ -14,7 +14,7 @@ set_units -time s
##################################################
# Create clock
##################################################
create_clock -name clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10} [get_ports {clk[0]}]
create_clock -name clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10} [get_ports {clk[0]}]
##################################################
# Create programmable clock
##################################################

6
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml
View File

@ -3,7 +3,7 @@
-->
<io_mapping>
<io name="gfpga_pad_GPIO_PAD[27:27]" net="a" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[15:15]" net="b" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[12:12]" net="c" dir="output"/>
<io name="gfpga_pad_GPIO_PAD[11:11]" net="a" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[14:14]" net="b" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[1:1]" net="c" dir="output"/>
</io_mapping>

4
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
View File

@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.4485172927
#0.4866067469
clk[0] <= !clk[0];
end
end
@ -109,7 +109,7 @@ initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#6.279242039
#6.812494755
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin

1117
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

File diff suppressed because it is too large Load Diff

118
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v
View File

@ -45,14 +45,14 @@ wire [0:0] clk_fm;
// ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[39] -----
assign gfpga_pad_GPIO_PAD_fm[39] = a[0];
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[22] -----
assign gfpga_pad_GPIO_PAD_fm[22] = a[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[48] -----
assign gfpga_pad_GPIO_PAD_fm[48] = b[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[26] -----
assign gfpga_pad_GPIO_PAD_fm[26] = b[0];
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[34] -----
assign c[0] = gfpga_pad_GPIO_PAD_fm[34];
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[9] -----
assign c[0] = gfpga_pad_GPIO_PAD_fm[9];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
@ -64,7 +64,6 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[6] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
@ -77,11 +76,9 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[19] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[20] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[21] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0;
@ -89,10 +86,12 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[31] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[32] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[33] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[34] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[42] = 1'b0;
@ -101,6 +100,7 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[45] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[46] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[47] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[48] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[49] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[50] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[51] = 1'b0;
@ -316,14 +316,14 @@ initial begin
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
@ -354,10 +354,10 @@ initial begin
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0001001000;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1110110111;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0010001000;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1101110111;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
@ -396,14 +396,14 @@ initial begin
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = {17{1'b0}};
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = {17{1'b1}};
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[0:16] = 17'b00000000110000001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_outb[0:16] = 17'b11111111001111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:3] = 4'b0001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:3] = 4'b1110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:3] = 4'b0010;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:3] = 4'b1101;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:2] = 3'b001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:2] = 3'b110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_1_D_0.mem_out[0:2] = 3'b001;
@ -434,10 +434,10 @@ initial begin
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:9] = 10'b0000110000;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:9] = 10'b1111001111;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:9] = 10'b0100010000;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:9] = 10'b1011101111;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:9] = 10'b0000000001;
force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:9] = 10'b1111111110;
force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
@ -458,8 +458,8 @@ initial begin
force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
@ -508,8 +508,8 @@ initial begin
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0] = 1'b1;
@ -586,8 +586,8 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
@ -624,8 +624,8 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00100100;
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11011011;
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:5] = 6'b010001;
@ -696,8 +696,8 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:7] = 8'b01000001;
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:7] = 8'b10111110;
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:7] = 8'b01000100;
force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:7] = 8'b10111011;
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:7] = 8'b00000001;
@ -752,8 +752,8 @@ initial begin
force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_top_track_12.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
@ -762,12 +762,12 @@ initial begin
force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = 2'b01;
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = 2'b10;
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@ -780,10 +780,10 @@ initial begin
force U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:7] = 8'b00010100;
force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:7] = 8'b11101011;
force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_out[0:7] = 8'b00011000;
force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:7] = 8'b11100111;
force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:7] = 8'b00000001;
force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:7] = 8'b11111110;
force U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_out[0:7] = 8'b00000001;
@ -828,8 +828,8 @@ initial begin
force U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
@ -900,10 +900,10 @@ initial begin
force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_7.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = 2'b01;
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = 2'b10;
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:1] = {2{1'b0}};
@ -914,8 +914,8 @@ initial begin
force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b010100;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b101011;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:5] = 6'b000001;
@ -940,8 +940,8 @@ initial begin
force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_1.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_1.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_1.mem_out[0:5] = 6'b010100;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_1.mem_outb[0:5] = 6'b101011;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_2.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_3.mem_out[0:5] = 6'b000001;
@ -1064,14 +1064,14 @@ initial begin
force U0_formal_verification.cby_2__2_.mem_left_ipin_7.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:5] = 6'b100100;
force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:5] = 6'b011011;
force U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_outb[0:5] = 6'b111110;
force U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_out[0:5] = 6'b001100;
force U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_outb[0:5] = 6'b110011;
force U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_out[0:5] = 6'b000001;
force U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_outb[0:5] = 6'b111110;
end

78
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -415,9 +415,9 @@
0
0
0
1
0
0
1
0
0
0
@ -457,13 +457,11 @@
0
0
0
1
0
0
0
0
0
0
1
0
0
0
@ -473,6 +471,8 @@
0
0
0
1
1
0
0
0
@ -613,26 +613,26 @@
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
@ -749,10 +749,10 @@
0
0
0
1
0
0
0
1
1
0
0
1
@ -767,13 +767,13 @@
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
@ -901,36 +901,39 @@
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
@ -940,11 +943,8 @@
0
0
0
1
0
0
1
0
0
0
1
@ -1083,10 +1083,10 @@
1
0
0
0
1
0
0
0
1
0
0
@ -1094,15 +1094,15 @@
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
@ -1327,11 +1327,11 @@
0
0
0
1
0
0
0
1
0
1
0
1
0
@ -1351,9 +1351,6 @@
0
0
0
1
1
1
0
0
0
@ -1369,12 +1366,10 @@
0
0
0
1
0
0
0
0
1
0
0
0
@ -1388,6 +1383,11 @@
0
0
0
1
1
0
0
0
0
0
0
@ -1945,8 +1945,8 @@
0
0
0
1
1
0
0
0
0
0
@ -2041,12 +2041,12 @@
0
0
0
1
0
0
0
1
0
0
1
0
0
0
@ -2255,7 +2255,7 @@
1
1
1
1
0
1
1
0
@ -2293,15 +2293,13 @@
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
@ -2319,6 +2317,8 @@
0
0
0
1
1
0
0
0
@ -2362,7 +2362,7 @@
1
1
1
0
1
1
1
1

116
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml
View File

@ -834,11 +834,11 @@
</bit>
<bit id="1958" value="0" path="fpga_top.sb_1__1_.mem_right_track_8.mem_out[0]">
</bit>
<bit id="1957" value="1" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[7]">
<bit id="1957" value="0" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[7]">
</bit>
<bit id="1956" value="0" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[6]">
</bit>
<bit id="1955" value="0" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[5]">
<bit id="1955" value="1" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[5]">
</bit>
<bit id="1954" value="0" path="fpga_top.sb_1__1_.mem_right_track_0.mem_out[4]">
</bit>
@ -918,7 +918,7 @@
</bit>
<bit id="1916" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
</bit>
<bit id="1915" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
<bit id="1915" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[9]">
</bit>
<bit id="1914" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[8]">
</bit>
@ -926,7 +926,7 @@
</bit>
<bit id="1912" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[6]">
</bit>
<bit id="1911" value="0" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[5]">
<bit id="1911" value="1" path="fpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[5]">
</bit>
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@ -934,11 +934,11 @@
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@ -2206,9 +2206,9 @@
</bit>
<bit id="1272" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[10]">
</bit>
<bit id="1271" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
<bit id="1271" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[9]">
</bit>
<bit id="1270" value="1" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
<bit id="1270" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[8]">
</bit>
<bit id="1269" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_DFFR_mem.mem_out[7]">
</bit>
@ -2658,15 +2658,15 @@
</bit>
<bit id="1046" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_3.mem_out[0]">
</bit>
<bit id="1045" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[5]">
<bit id="1045" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[5]">
</bit>
<bit id="1044" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[4]">
</bit>
<bit id="1043" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[3]">
<bit id="1043" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[3]">
</bit>
<bit id="1042" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[2]">
</bit>
<bit id="1041" value="1" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[1]">
<bit id="1041" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[1]">
</bit>
<bit id="1040" value="0" path="fpga_top.cbx_2__0_.mem_top_ipin_2.mem_out[0]">
</bit>
@ -2706,11 +2706,11 @@
</bit>
<bit id="1022" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_3.mem_out[0]">
</bit>
<bit id="1021" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[1]">
<bit id="1021" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[1]">
</bit>
<bit id="1020" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[0]">
<bit id="1020" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_2.mem_out[0]">
</bit>
<bit id="1019" value="1" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[1]">
<bit id="1019" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[1]">
</bit>
<bit id="1018" value="0" path="fpga_top.cbx_2__0_.mem_bottom_ipin_1.mem_out[0]">
</bit>
@ -2742,7 +2742,7 @@
</bit>
<bit id="1004" value="0" path="fpga_top.sb_2__0_.mem_left_track_9.mem_out[0]">
</bit>
<bit id="1003" value="1" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[1]">
<bit id="1003" value="0" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[1]">
</bit>
<bit id="1002" value="0" path="fpga_top.sb_2__0_.mem_left_track_7.mem_out[0]">
</bit>
@ -2752,7 +2752,7 @@
</bit>
<bit id="999" value="0" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[1]">
</bit>
<bit id="998" value="1" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[0]">
<bit id="998" value="0" path="fpga_top.sb_2__0_.mem_left_track_3.mem_out[0]">
</bit>
<bit id="997" value="0" path="fpga_top.sb_2__0_.mem_left_track_1.mem_out[1]">
</bit>
@ -2770,9 +2770,9 @@
</bit>
<bit id="990" value="0" path="fpga_top.sb_2__0_.mem_top_track_14.mem_out[0]">
</bit>
<bit id="989" value="0" path="fpga_top.sb_2__0_.mem_top_track_12.mem_out[1]">
<bit id="989" value="1" path="fpga_top.sb_2__0_.mem_top_track_12.mem_out[1]">
</bit>
<bit id="988" value="0" path="fpga_top.sb_2__0_.mem_top_track_12.mem_out[0]">
<bit id="988" value="1" path="fpga_top.sb_2__0_.mem_top_track_12.mem_out[0]">
</bit>
<bit id="987" value="0" path="fpga_top.sb_2__0_.mem_top_track_10.mem_out[1]">
</bit>
@ -3894,9 +3894,9 @@
</bit>
<bit id="428" value="0" path="fpga_top.sb_0__0_.mem_right_track_4.mem_out[0]">
</bit>
<bit id="427" value="1" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[1]">
<bit id="427" value="0" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[1]">
</bit>
<bit id="426" value="1" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[0]">
<bit id="426" value="0" path="fpga_top.sb_0__0_.mem_right_track_2.mem_out[0]">
</bit>
<bit id="425" value="0" path="fpga_top.sb_0__0_.mem_right_track_0.mem_out[1]">
</bit>
@ -4086,17 +4086,17 @@
</bit>
<bit id="332" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_9.mem_out[0]">
</bit>
<bit id="331" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[7]">
<bit id="331" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[7]">
</bit>
<bit id="330" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[6]">
</bit>
<bit id="329" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[5]">
<bit id="329" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[5]">
</bit>
<bit id="328" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[4]">
</bit>
<bit id="327" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[3]">
</bit>
<bit id="326" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[2]">
<bit id="326" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[2]">
</bit>
<bit id="325" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_1.mem_out[1]">
</bit>
@ -4514,7 +4514,7 @@
</bit>
<bit id="118" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
</bit>
<bit id="117" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
<bit id="117" value="0" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
</bit>
<bit id="116" value="1" path="fpga_top.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
</bit>
@ -4590,15 +4590,15 @@
</bit>
<bit id="80" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_2.mem_out[0]">
</bit>
<bit id="79" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[5]">
<bit id="79" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[5]">
</bit>
<bit id="78" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[4]">
</bit>
<bit id="77" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[3]">
<bit id="77" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[3]">
</bit>
<bit id="76" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[2]">
</bit>
<bit id="75" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[1]">
<bit id="75" value="1" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[1]">
</bit>
<bit id="74" value="0" path="fpga_top.cbx_2__2_.mem_bottom_ipin_1.mem_out[0]">
</bit>
@ -4638,9 +4638,9 @@
</bit>
<bit id="56" value="0" path="fpga_top.sb_2__2_.mem_left_track_5.mem_out[0]">
</bit>
<bit id="55" value="0" path="fpga_top.sb_2__2_.mem_left_track_3.mem_out[1]">
<bit id="55" value="1" path="fpga_top.sb_2__2_.mem_left_track_3.mem_out[1]">
</bit>
<bit id="54" value="0" path="fpga_top.sb_2__2_.mem_left_track_3.mem_out[0]">
<bit id="54" value="1" path="fpga_top.sb_2__2_.mem_left_track_3.mem_out[0]">
</bit>
<bit id="53" value="0" path="fpga_top.sb_2__2_.mem_left_track_1.mem_out[1]">
</bit>
@ -4728,7 +4728,7 @@
</bit>
<bit id="11" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
</bit>
<bit id="10" value="0" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
<bit id="10" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
</bit>
<bit id="9" value="1" path="fpga_top.grid_io_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem.mem_out[0]">
</bit>

422
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
View File

File diff suppressed because it is too large Load Diff

2
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc
View File

@ -14,7 +14,7 @@ set_units -time s
##################################################
# Create clock
##################################################
create_clock -name clk[0] -period 8.970345577e-10 -waveform {0 4.485172789e-10} [get_ports {clk[0]}]
create_clock -name clk[0] -period 9.732135098e-10 -waveform {0 4.866067549e-10} [get_ports {clk[0]}]
##################################################
# Create programmable clock
##################################################

6
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/pin_mapping.xml
View File

@ -3,7 +3,7 @@
-->
<io_mapping>
<io name="gfpga_pad_GPIO_PAD[39:39]" net="a" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[48:48]" net="b" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[34:34]" net="c" dir="output"/>
<io name="gfpga_pad_GPIO_PAD[22:22]" net="a" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[26:26]" net="b" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[9:9]" net="c" dir="output"/>
</io_mapping>

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 90ee6e663a0e021604dff4552f5b7f9744cedd74
Subproject commit 0963c20472e178d6562e40d90727870342035f67