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[Tool] Bug fix for mappable I/O support

This commit is contained in:
tangxifan 2020-11-04 20:45:51 -07:00
parent a6c7bb2c48
commit 9b0617ffe6
2 changed files with 20 additions and 10 deletions
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5
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -159,6 +159,11 @@ void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager,
const CircuitPortId& circuit_port) {
BasicPort module_port(generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, primitive_model, circuit_port), circuit_lib.port_size(circuit_port));
ModulePortId primitive_io_port_id = module_manager.add_port(primitive_module, module_port, module_io_port_type);
/* Set if the port is mappable or not */
if (true == circuit_lib.port_is_data_io(circuit_port)) {
module_manager.set_port_is_mappable_io(primitive_module, primitive_io_port_id, true);
}
ModulePortId logic_io_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(circuit_port));
BasicPort logic_io_port = module_manager.module_port(logic_module, logic_io_port_id);
VTR_ASSERT(logic_io_port.get_width() == module_port.get_width());

25
openfpga/src/utils/module_manager_utils.cpp
View File

@ -157,20 +157,29 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
*/
for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) {
BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
ModulePortId module_port = ModulePortId::INVALID();
if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
&& (false == circuit_lib.port_is_io(port)) ) {
module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);
module_port = module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);
} else if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) {
module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);
module_port = module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);
} else if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
&& (true == circuit_lib.port_is_io(port)) ) {
module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT);
module_port = module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT);
} else if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) {
VTR_ASSERT(true == circuit_lib.port_is_io(port));
module_manager.add_port(module, port_info, ModuleManager::MODULE_GPOUT_PORT);
module_port = module_manager.add_port(module, port_info, ModuleManager::MODULE_GPOUT_PORT);
} else if ( (CIRCUIT_MODEL_PORT_INOUT == circuit_lib.port_type(port))
&& (true == circuit_lib.port_is_io(port)) ) {
module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIO_PORT);
module_port = module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIO_PORT);
}
/* Specify if the port can be mapped to an data signal */
if (true == module_manager.valid_module_port_id(module, module_port)) {
if (true == circuit_lib.port_is_data_io(port)) {
module_manager.set_port_is_mappable_io(module, module_port, true);
}
}
}
@ -191,11 +200,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
for (const auto& kv : port_type2type_map) {
for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) {
BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
ModulePortId module_port = module_manager.add_port(module, port_info, kv.second);
/* Specify if the port can be mapped to an data signal */
if (true == circuit_lib.port_is_data_io(port)) {
module_manager.set_port_is_mappable_io(module, module_port, true);
}
module_manager.add_port(module, port_info, kv.second);
}
}