From 9adeb550dc60d25aa9e9caa9b4ab9d996200c067 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:28:00 -0600 Subject: [PATCH] [OpenFPGA Tool] Bug fix in fabric builder --- openfpga/src/fabric/build_memory_modules.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp index b9b83508a..32d1c93b2 100644 --- a/openfpga/src/fabric/build_memory_modules.cpp +++ b/openfpga/src/fabric/build_memory_modules.cpp @@ -636,13 +636,13 @@ void build_frame_memory_module(ModuleManager& module_manager, module_manager.add_configurable_child(mem_module, sram_mem_module, sram_instance); /* Wire data_in port to SRAM BL port */ - ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_bl_ports[0])); + ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_bl_ports[0])); add_module_bus_nets(module_manager, mem_module, mem_module, 0, mem_data_port, sram_mem_module, sram_instance, sram_bl_port); /* Wire decoder data_out port to sram WL ports */ - ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wl_ports[0])); + ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_wl_ports[0])); ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); ModuleNetId wl_net = module_manager.create_module_net(mem_module); /* Source node of the input net is the input of memory module */