[Doc] Add fabric bitstream file format for QL memory bank
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@ -65,6 +65,112 @@ The information depends on the type of configuration procotol.
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.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
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.. option:: ql_memory_bank using decoders
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Multiple lines will be included, each of which is organized as <bl_address><wl_address><bits>.
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The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream width (LSB -> MSB): <bl_address 5 bits><wl_address 5 bits><data input 1 bits>
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The first part represents the Bit-Line address.
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The second part represents the Word-Line address.
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The third part represents the configuration bit.
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For example
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.. code-block:: xml
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<bitline_address><wordline_address><bit_value>
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<bitline_address><wordline_address><bit_value>
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...
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<bitline_address><wordline_address><bit_value>
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.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
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.. option:: ql_memory_bank using flatten BL and WLs
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Multiple lines will be included, each of which is organized as <bl_data><wl_data>.
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The size of data are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream width (LSB -> MSB): <Region 1: bl_data 5 bits><Region 2: bl_data 4 bits><Region 1: wl_data 5 bits><Region 2: wl_data 6 bits>
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The first part represents the Bit-Line data from multiple configuration regions.
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The second part represents the Word-Line data from multiple configuration regions.
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For example
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.. code-block:: xml
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<bitline_data_region1><bitline_data_region2><wordline_data_region1><wordline_data_region2>
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<bitline_data_region1><bitline_data_region2><wordline_data_region1><wordline_data_region2>
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...
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<bitline_data_region1><bitline_data_region2><wordline_data_region1><wordline_data_region2>
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.. note:: The WL data of region is one-hot.
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.. option:: ql_memory_bank using shift registers
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Multiple lines will be included, each of which is organized as <bl_data> or <wl_data>.
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The size of data are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream word count: 36
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// Bitstream bl word size: 39
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// Bitstream wl word size: 37
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// Bitstream width (LSB -> MSB): <bl shift register heads 1 bits><wl shift register heads 1 bits>
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The bitstream data are organized by words. Each word consists of two parts, BL data to be loaded to BL shift register chains and WL data to be loaded to WL shift register chains
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For example
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.. code-block:: xml
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// Word 0
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// BL Part
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<bitline_shift_register_data@clock_0> ----
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<bitline_shift_register_data@clock_1> ^
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<bitline_shift_register_data@clock_1> |
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... BL word size
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<bitline_shift_register_data@clock_n-2> |
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<bitline_shift_register_data@clock_n-1> v
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<bitline_shift_register_data@clock_n> ----
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// Word 0
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// WL Part
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<wordline_shift_register_data@clock_0> ----
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<wordline_shift_register_data@clock_1> ^
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<wordline_shift_register_data@clock_1> |
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... WL word size
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<wordline_shift_register_data@clock_n-2> |
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<wordline_shift_register_data@clock_n-1> v
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<wordline_shift_register_data@clock_n> ----
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// Word 1
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// BL Part
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<bitline_shift_register_data@clock_0> ----
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<bitline_shift_register_data@clock_1> ^
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<bitline_shift_register_data@clock_1> |
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... BL word size
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<bitline_shift_register_data@clock_n-2> |
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<bitline_shift_register_data@clock_n-1> v
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<bitline_shift_register_data@clock_n> ----
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// Word 1
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// WL Part
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<wordline_shift_register_data@clock_0> ----
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<wordline_shift_register_data@clock_1> ^
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<wordline_shift_register_data@clock_1> |
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... WL word size
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<wordline_shift_register_data@clock_n-2> |
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<wordline_shift_register_data@clock_n-1> v
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<wordline_shift_register_data@clock_n> ----
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... // More words
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.. note:: The BL/WL data may be multi-bit, while each bit corresponds to a configuration region
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.. note:: The WL data of region is one-hot.
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.. option:: frame_based
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Multiple lines will be included, each of which is organized as ``<address><data_input_bits>``.
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