From 2019840d7cc0b035b1c4f2a8d68c19c63ea240f4 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 13 May 2019 14:45:02 -0600 Subject: [PATCH] cleaned unused variables --- vpr7_x2p/vpr/SRC/base/draw.c | 6 ++--- vpr7_x2p/vpr/SRC/base/vpr_api.c | 3 ++- .../fpga_x2p/base/fpga_x2p_bitstream_utils.c | 5 +--- .../SRC/fpga_x2p/base/fpga_x2p_lut_utils.c | 2 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 7 +++++- .../SRC/fpga_x2p/base/fpga_x2p_timing_utils.c | 2 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 17 +++++++++++--- .../clb_pin_remap/clb_pin_remap_util.c | 2 -- .../clb_pin_remap/post_place_timing.c | 8 ------- .../fpga_x2p/router/fpga_x2p_pb_rr_graph.c | 4 +--- vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c | 1 - .../SRC/fpga_x2p/spice/spice_grid_testbench.c | 1 - .../vpr/SRC/fpga_x2p/spice/spice_pbtypes.c | 11 --------- .../vpr/SRC/fpga_x2p/spice/spice_primitive.c | 16 ------------- .../spice/spice_primitive_testbench.c | 1 - .../SRC/fpga_x2p/verilog/verilog_decoder.c | 2 +- .../verilog_formal_random_top_testbench.c | 22 ++++-------------- .../verilog/verilog_formality_autodeck.c | 4 ---- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 19 ++------------- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 6 ----- .../SRC/fpga_x2p/verilog/verilog_routing.c | 6 ++--- .../vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 10 +++----- .../fpga_x2p/verilog/verilog_sdc_pb_types.c | 21 ++++++----------- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 7 +++--- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 5 ++-- vpr7_x2p/vpr/SRC/main.c | 5 ++++ vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c | 23 ------------------- vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c | 1 - vpr7_x2p/vpr/SRC/pack/cluster_legality.c | 3 +-- vpr7_x2p/vpr/SRC/pack/pb_type_graph.c | 2 -- vpr7_x2p/vpr/SRC/place/place.c | 9 +++----- vpr7_x2p/vpr/SRC/place/place_macro.c | 3 +-- .../vpr/SRC/route/pb_pin_eq_auto_detect.c | 2 +- vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c | 1 - vpr7_x2p/vpr/SRC/util/vpr_utils.c | 2 -- 35 files changed, 65 insertions(+), 174 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/draw.c b/vpr7_x2p/vpr/SRC/base/draw.c index 2b66c5992..59ceb1a31 100755 --- a/vpr7_x2p/vpr/SRC/base/draw.c +++ b/vpr7_x2p/vpr/SRC/base/draw.c @@ -2039,8 +2039,8 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node) { static void draw_pin_to_pin(int opin_node, int ipin_node) { /* This routine draws an edge from the opin rr node to the ipin rr node */ - int opin_grid_x, opin_grid_y, opin_pin_num, opin; - int ipin_grid_x, ipin_grid_y, ipin_pin_num, ipin; + int opin_grid_x, opin_grid_y, opin; + int ipin_grid_x, ipin_grid_y, ipin; int ofs, pin_ofs; boolean found; float x1, x2, y1, y2; @@ -2060,7 +2060,6 @@ static void draw_pin_to_pin(int opin_node, int ipin_node) { opin_grid_y = rr_node[opin_node].ylow; opin_grid_y = opin_grid_y - grid[opin_grid_x][opin_grid_y].offset; opin = rr_node[opin_node].ptc_num; - opin_pin_num = rr_node[opin_node].ptc_num; type = grid[opin_grid_x][opin_grid_y].type; found = FALSE; @@ -2083,7 +2082,6 @@ static void draw_pin_to_pin(int opin_node, int ipin_node) { ipin_grid_y = rr_node[ipin_node].ylow; ipin_grid_y = ipin_grid_y - grid[ipin_grid_x][ipin_grid_y].offset; ipin = rr_node[ipin_node].ptc_num; - ipin_pin_num = rr_node[ipin_node].ptc_num; type = grid[ipin_grid_x][ipin_grid_y].type; found = FALSE; diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 24fa4ed77..82153e26d 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -563,9 +563,10 @@ void vpr_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch arch) { fflush(stdout); /* Close down X Display */ + /* TODO: DANGEROUS way of coding, clean up */ if (vpr_setup.ShowGraphics) close_graphics(); - free_draw_structs(); + free_draw_structs(); } /* Free architecture data structures */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c index b4e83160d..fde3b52c7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c @@ -1147,7 +1147,7 @@ add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, int num_bls, int num_wls, int* bl_conf_bits, int* wl_conf_bits) { - int ibit, cur_bl, cur_wl, cur_mem_bit; + int ibit, cur_bl, cur_wl; t_spice_model* cur_sram_spice_model = NULL; t_conf_bit* bl_bit = NULL; t_conf_bit* wl_bit = NULL; @@ -1157,7 +1157,6 @@ void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, i assert(NULL != cur_sram_orgz_info); /* Get current counter of sram_spice_model */ - cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); /* Get memory model */ @@ -1423,13 +1422,11 @@ void determine_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_orgz_info, OUTP int* num_array_bl, OUTP int* num_array_wl, OUTP int* bl_decoder_size, OUTP int* wl_decoder_size) { t_spice_model* mem_model = NULL; - int num_mem_bit; int num_reserved_bl, num_reserved_wl; /* Check */ assert(SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type); - num_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); get_sram_orgz_info_num_blwl(cur_sram_orgz_info, num_array_bl, num_array_wl); get_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, &num_reserved_bl, &num_reserved_wl); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.c index 2e7b38ece..2e38bb305 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.c @@ -380,7 +380,7 @@ char** get_wired_lut_truth_table() { char** assign_post_routing_wired_lut_truth_table(int lut_output_vpack_net_num, int lut_size, int* lut_pin_vpack_net_num, int* truth_table_length) { - int inet, iport; + int inet; char** tt = (char**) my_malloc(sizeof(char*)); /* truth_table_length will be always 1*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 8c828ac71..900a42dd1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -948,7 +948,12 @@ void check_keywords_conflict(t_arch Arch) { vpr_printf(TIO_MESSAGE_ERROR, "Found %d conflicted keywords!\n", conflict); exit(1); } - + + /* Free the memory of the keywords after the checking */ + for (i = 0 ; cur < num_keyword ; i++) { + my_free(keywords[cur]); + } + return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.c index db867daa1..64955faa2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.c @@ -248,7 +248,7 @@ void configure_tedges_delay_matrix(enum spice_model_delay_type delay_type, /* allocate and parse delay_matix */ float** fpga_spice_atof_2D(int num_in_port, int num_out_port, char* str) { - int i, j; + int i; float** delay_matrix = NULL; /* allocate */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index b76bf91d2..96bf2176a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -389,8 +389,6 @@ void config_one_spice_model_buffer(int num_spice_models, void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, t_spice_model* spice_model) { int i; - t_spice_model* inv_spice_model = NULL; - t_spice_model* buf_spice_model = NULL; t_spice_model* pgl_spice_model = NULL; for (i = 0; i < num_spice_models; i++) { @@ -3511,4 +3509,17 @@ void get_fpga_x2p_global_all_clock_ports(t_llist* head, return; } - + +/* Returns the number of char occupied by the int */ +int my_strlen_int(int input_int) { + + int length_input; + char* input_str; + + input_str = my_itoa(input_int); + length_input = strlen(input_str); + + free(input_str); + + return length_input; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.c b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.c index 4ffe685e2..8924029f9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.c @@ -659,7 +659,6 @@ void rec_update_net_info_local_rr_node_tree(t_pb* src_pb, int src_node_index) { int ipb, jpb, iedge, to_node, mode_index; t_rr_node* local_rr_graph = NULL; - t_pb_graph_pin* src_pb_graph_pin = NULL; t_pb_graph_pin* des_pb_graph_pin = NULL; t_pb_type* src_pb_type = NULL; @@ -675,7 +674,6 @@ void rec_update_net_info_local_rr_node_tree(t_pb* src_pb, if ((src_node_index == local_rr_graph[to_node].prev_node)&&(iedge == local_rr_graph[to_node].prev_edge) /* Make sure in the same mode */ &&(mode_index == local_rr_graph[to_node].pb_graph_pin->parent_node->pb_type->parent_mode->index)) { - src_pb_graph_pin = local_rr_graph[src_node_index].pb_graph_pin; des_pb_graph_pin = local_rr_graph[to_node].pb_graph_pin; local_rr_graph[to_node].net_num = local_rr_graph[src_node_index].net_num; /* Update recursively */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.c index e5bb1896f..486f902ea 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.c @@ -262,19 +262,11 @@ float esti_distance_num_seg_delay(int distance, int num_segment, t_segment_inf* segment_inf, int allow_long_segment) { - int actual_distance; float esti_delay = 0.; float min_out_range_esti_delay = 0.; float max_in_range_esti_delay = 0.; int iseg, min_out_range_seg, max_in_range_seg; - /* Min-distance should be 1 */ - if (distance < 1) { - actual_distance = 1; - } else { - actual_distance = distance; - } - /* Find the min-length segment whose length is larger than distance */ min_out_range_seg = -1; for (iseg = 0; iseg < num_segment; iseg++) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c index e361e8191..1993a6ecd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c @@ -1254,7 +1254,7 @@ void rec_add_rr_graph_wired_lut_rr_edges(INP t_pb* cur_op_pb, * As so, edges have to be added to the decendents of sources */ int add_virtual_sources_to_rr_graph_multi_sources(t_rr_graph* local_rr_graph) { - int inet, isrc, iedge, to_node; + int inet, isrc; int unique_src_node; int cnt = 0; @@ -1282,8 +1282,6 @@ int add_virtual_sources_to_rr_graph_multi_sources(t_rr_graph* local_rr_graph) { /* Connect edges to sources */ local_rr_graph->rr_node[unique_src_node].edges[isrc] = local_rr_graph->net_rr_sources[inet][isrc]; local_rr_graph->rr_node[unique_src_node].switches[isrc] = DEFAULT_SWITCH_ID; - /* Configure the original sources */ - to_node = local_rr_graph->net_rr_sources[inet][isrc]; } /* Replace the sources with the new source node */ local_rr_graph->net_num_sources[inet] = 1; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c index 386331e90..0fa02abeb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c @@ -115,7 +115,6 @@ char* convert_option_mandatory_to_str(enum opt_manda cur) { void print_opt_info_help_desk(t_opt_info* cur_opt_info) { int max_str_len = -1; - int offset; t_opt_info* cur = cur_opt_info; char* str_fixed_len = NULL; char* name_tag = "Option Names"; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.c index 4061d633d..108e62efe 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.c @@ -424,7 +424,6 @@ int fprint_spice_one_grid_testbench(char* formatted_spice_dir, char* temp_include_file_path = NULL; char* title = my_strcat("FPGA Grid Testbench for Design: ", circuit_name); char* grid_testbench_file_path = my_strcat(formatted_spice_dir, grid_test_bench_name); - t_llist* temp = NULL; int used = 0; /* Check if the path exists*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.c index fa1c180f9..79b3cf72e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.c @@ -398,7 +398,6 @@ void fprintf_spice_pb_graph_pin_interc(FILE* fp, t_pb_type* src_pb_type = NULL; /* int src_pb_type_index = -1; */ - t_pb_graph_node* des_pb_graph_node = NULL; /* t_pb_type* des_pb_type = NULL; */ /* int des_pb_type_index = -1; */ @@ -465,7 +464,6 @@ void fprintf_spice_pb_graph_pin_interc(FILE* fp, src_pb_type = src_pb_graph_node->pb_type; /* src_pb_type_index = src_pb_graph_node->placement_index; */ /* Des pin, node, pb_type */ - des_pb_graph_node = des_pb_graph_pin->parent_node; /* des_pb_type = des_pb_graph_node->pb_type; */ /* des_pb_type_index = des_pb_graph_node->placement_index; */ /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ @@ -527,7 +525,6 @@ void fprintf_spice_pb_graph_pin_interc(FILE* fp, src_pb_type = src_pb_graph_node->pb_type; /* src_pb_type_index = src_pb_graph_node->placement_index; */ /* Des pin, node, pb_type */ - des_pb_graph_node = des_pb_graph_pin->parent_node; /* des_pb_type = des_pb_graph_node->pb_type; */ /* des_pb_type_index = des_pb_graph_node->placement_index; */ /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ @@ -1148,7 +1145,6 @@ void fprint_spice_pb_graph_node_rec(FILE* fp, char* child_pb_type_prefix = NULL; char* subckt_port_prefix = NULL; - t_pb* child_pb = NULL; /* Check the file handler*/ if (NULL == fp) { @@ -1201,7 +1197,6 @@ void fprint_spice_pb_graph_node_rec(FILE* fp, /* Special care for LUT !!! * Mapped logical block information is stored in child_pbs */ - child_pb = get_lut_child_pb(cur_pb, mode_index); /* fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, child_pb, cur_pb_graph_node, @@ -1218,7 +1213,6 @@ void fprint_spice_pb_graph_node_rec(FILE* fp, */ break; case MEMORY_CLASS: - child_pb = get_hardlogic_child_pb(cur_pb, mode_index); /* Consider the num_pb, create all the subckts*/ /* fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, @@ -2031,9 +2025,7 @@ void fprint_grid_physical_blocks(char* subckt_dir, t_arch* arch) { int subckt_name_str_len = 0; char* subckt_name = NULL; - t_block* mapped_block = NULL; int iz; - int cur_block_index = 0; int capacity; FILE* fp = NULL; char* fname = NULL; @@ -2078,7 +2070,6 @@ void fprint_grid_physical_blocks(char* subckt_dir, ix, iy); } - cur_block_index = 0; /* check capacity and if this has been mapped */ for (iz = 0; iz < capacity; iz++) { /* Comments: Grid [x][y]*/ @@ -2124,8 +2115,6 @@ void fprint_grid_physical_blocks(char* subckt_dir, } else { fprint_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); } - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - mapped_block = search_mapped_block(ix, iy, iz); /* Local Vdd and Gnd, subckt name*/ fprintf(fp, "+ svdd sgnd %s\n", get_grid_phy_block_subckt_name(ix, iy, iz, subckt_name, NULL)); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.c index a439e03c0..1f21995d7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.c @@ -39,23 +39,13 @@ void fprint_pb_primitive_generic(FILE* fp, t_pb_type* prim_pb_type, int index, t_spice_model* spice_model) { - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - int num_output_port = 0; - t_spice_model_port** output_ports = NULL; - int num_clock_port = 0; - t_spice_model_port** clock_ports = NULL; int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - t_spice_model_port* regular_sram_port = NULL; - t_spice_model_port* mode_bit_port = NULL; int i; int num_sram = 0; int expected_num_sram = 0; int* sram_bits = NULL; int cur_num_sram = 0; - t_spice_model* mem_model = NULL; int mapped_logical_block_index = OPEN; char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ @@ -74,12 +64,6 @@ void fprint_pb_primitive_generic(FILE* fp, ||(SPICE_MODEL_HARDLOGIC == spice_model->type) ||(SPICE_MODEL_IOPAD == spice_model->type)); - /* Find ports*/ - input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - clock_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, TRUE); - sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - /* Find mapped logical block */ if (NULL != prim_phy_pb) { for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.c index e3dfa4f19..07ede11e0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.c @@ -114,7 +114,6 @@ void fprint_spice_primitive_testbench_call_one_primitive(FILE* fp, t_spice_model_port** input_ports = NULL; int num_output_port = 0; t_spice_model_port** output_ports = NULL; - int num_inout_port = 0; t_spice_model_port** inout_ports = NULL; int num_clk_port = 0; t_spice_model_port** clk_ports = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c index 91acabf24..731148c50 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c @@ -292,7 +292,7 @@ void dump_verilog_standalone_sram_config_module(FILE* fp, static void dump_verilog_scan_chain_config_module(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info) { - int i, num_mem_bits; + int num_mem_bits; /* Check */ assert(SPICE_SRAM_SCAN_CHAIN == cur_sram_orgz_info->type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c index 7cf108756..8c892e279 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c @@ -56,10 +56,9 @@ void dump_verilog_top_random_testbench_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, t_syn_verilog_opts fpga_verilog_opts){ - int iblock, iopad_idx; + int iblock; boolean bench_as_clk = FALSE; t_spice_model* mem_model = NULL; - char* port_name = NULL; get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); @@ -71,7 +70,6 @@ void dump_verilog_top_random_testbench_ports(FILE* fp, for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -89,7 +87,6 @@ void dump_verilog_top_random_testbench_ports(FILE* fp, for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -103,7 +100,6 @@ void dump_verilog_top_random_testbench_ports(FILE* fp, for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -117,7 +113,6 @@ void dump_verilog_top_random_testbench_ports(FILE* fp, for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -133,7 +128,7 @@ void dump_verilog_top_random_testbench_ports(FILE* fp, static void dump_verilog_top_random_testbench_call_benchmark(FILE* fp, char* reference_verilog_top_name){ - int iblock, iopad_idx; + int iblock; fprintf(fp, "`ifdef %s\n", autochecked_simulation_flag); fprintf(fp, "// Reference Benchmark instanciation\n"); @@ -142,7 +137,6 @@ void dump_verilog_top_random_testbench_call_benchmark(FILE* fp, for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -207,12 +201,11 @@ void dump_verilog_timeout_and_vcd(FILE * fp, static void dump_verilog_top_random_testbench_check(FILE* fp){ - int iblock, iopad_idx; + int iblock; fprintf(fp, " // Begin checking\n"); fprintf(fp, " always@(negedge %s) begin\n", clock_input_name); for (iblock = 0; iblock < num_logical_blocks; iblock++) { if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -229,7 +222,6 @@ void dump_verilog_top_random_testbench_check(FILE* fp){ fprintf(fp, " end\n\n"); for (iblock = 0; iblock < num_logical_blocks; iblock++) { if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -252,7 +244,7 @@ void dump_verilog_top_random_testbench_check(FILE* fp){ static void dump_verilog_random_testbench_call_top_module(FILE* fp, char* circuit_name) { - int iblock, iopad_idx; + int iblock; fprintf(fp, "// GFPGA instanciation\n"); fprintf(fp, " %s%s DUT(\n", circuit_name, formal_verification_top_postfix); @@ -260,7 +252,6 @@ void dump_verilog_random_testbench_call_top_module(FILE* fp, for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -283,15 +274,13 @@ void dump_verilog_random_testbench_call_top_module(FILE* fp, static void dump_verilog_top_random_stimuli(FILE* fp, t_spice verilog){ - int iblock, iopad_idx; - char* reset_input_name = NULL; + int iblock; fprintf(fp, "//----- Initialization\n"); fprintf(fp, " initial begin\n"); for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); @@ -331,7 +320,6 @@ void dump_verilog_top_random_stimuli(FILE* fp, for (iblock = 0; iblock < num_logical_blocks; iblock++) { /* General INOUT*/ if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; /* Make sure We find the correct logical block !*/ assert((VPACK_INPAD == logical_block[iblock].type) ||(VPACK_OUTPAD == logical_block[iblock].type)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c index 569d6cac2..db4de023d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c @@ -77,11 +77,9 @@ static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chompe } static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){ - t_phy_pb* cur_phy_pb; t_pb* pb; char* inst_name = NULL; const t_pb_type *pb_type; - t_pb_graph_node *pb_graph_node; t_mode *mode; int i, j, x_pos, y_pos; char* grid_x = NULL; @@ -90,11 +88,9 @@ static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){ x_pos = block[h].x; y_pos = block[h].y; - cur_phy_pb = (t_phy_pb*) block[h].phy_pb; pb = (t_pb*) block[h].pb; pb_type = pb->pb_graph_node->pb_type; - pb_graph_node = pb->pb_graph_node; mode = &pb_type->modes[pb->mode]; grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_")); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 67447c3ed..452928472 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1021,7 +1021,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode) { - int i, iedge, ipin; + int iedge, ipin; int fan_in = 0; t_interconnect* cur_interc = NULL; enum e_interconnect verilog_interc_type = DIRECT_INTERC; @@ -1030,16 +1030,12 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_node* src_pb_graph_node = NULL; t_pb_type* src_pb_type = NULL; - t_pb_graph_node* des_pb_graph_node = NULL; - char* formatted_parent_pin_prefix = chomp_verilog_prefix(parent_pin_prefix); /* Complete a "_" at the end if needed*/ char* src_pin_prefix = NULL; char* des_pin_prefix = NULL; - int num_mux_sram_bits = 0; int* mux_sram_bits = NULL; int cur_num_sram = 0; - int mux_level = 0; int num_mux_conf_bits = 0; int num_mux_reserved_conf_bits = 0; int cur_bl, cur_wl; @@ -1101,7 +1097,6 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, src_pb_graph_node = src_pb_graph_pin->parent_node; src_pb_type = src_pb_graph_node->pb_type; /* Des pin, node, pb_type */ - des_pb_graph_node = des_pb_graph_pin->parent_node; /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ generate_verilog_src_des_pb_graph_pin_prefix(src_pb_graph_pin, des_pb_graph_pin, pin2pin_interc_type, cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); @@ -1159,7 +1154,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, hierarchical_name = ""; mux_name = (char *) my_malloc(sizeof(char)*(strlen(cur_interc->spice_model->name) - + 5 + strlen(my_itoa(fan_in)) + 1 + strlen(my_itoa(cur_interc->spice_model->cnt + 2)))); + + 5 + strlen(my_itoa(fan_in)) + 1 + strlen(my_itoa(cur_interc->spice_model->cnt)) + 2)); sprintf(mux_name, "%s_size%d_%d_", cur_interc->spice_model->name, fan_in, cur_interc->spice_model->cnt); @@ -1178,8 +1173,6 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, src_pb_graph_node = src_pb_graph_pin->parent_node; src_pb_type = src_pb_graph_node->pb_type; - /* Des pin, node, pb_type */ - des_pb_graph_node = des_pb_graph_pin->parent_node; /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ generate_verilog_src_des_pb_graph_pin_prefix(src_pb_graph_pin, des_pb_graph_pin, pin2pin_interc_type, cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); @@ -1217,10 +1210,6 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, cur_sram_orgz_info->type, fan_in); - /* Get the number of SRAM bits required by this MUX */ - num_mux_sram_bits = count_num_sram_bits_one_spice_model(cur_interc->spice_model, - fan_in); - /* Dump the configuration port bus */ dump_verilog_mux_config_bus(fp, cur_interc->spice_model, cur_sram_orgz_info, fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); @@ -1381,8 +1370,6 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, t_mode* cur_mode = NULL; t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; t_pb_graph_node* child_pb_graph_node = NULL; - t_pb* child_pb = NULL; - int is_child_pb_idle = 0; char* formatted_pin_prefix = format_verilog_node_prefix(pin_prefix); /* Complete a "_" at the end if needed*/ @@ -1591,11 +1578,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, int child_pb_num_conf_bits = 0; int child_pb_num_iopads = 0; - t_spice_model* mem_model = NULL; int num_reserved_conf_bits = 0; int num_conf_bits = 0; int stamped_sram_cnt = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - int stamped_sram_lsb = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); int stamped_iopad_cnt = iopad_verilog_model->cnt; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index cda30f670..22765eaed 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -67,8 +67,6 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, t_spice_model_port** bl_port = NULL; int num_wl_ports = 0; t_spice_model_port** wl_port = NULL; - int num_bl_per_sram = 0; - int num_wl_per_sram = 0; int cur_num_sram = 0; int num_conf_bits = 0; @@ -199,8 +197,6 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); assert(1 == num_bl_ports); assert(1 == num_wl_ports); - num_bl_per_sram = bl_port[0]->size; - num_wl_per_sram = wl_port[0]->size; break; case SPICE_SRAM_STANDALONE: case SPICE_SRAM_SCAN_CHAIN: @@ -421,7 +417,6 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, int num_lut_sram = 0; int num_mode_sram = 0; t_spice_model_port* lut_sram_port = NULL; - t_spice_model_port* mode_bit_port = NULL; int num_pb_type_input_port = 0; t_port** pb_type_input_ports = NULL; @@ -478,7 +473,6 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, assert (num_lut_sram == (int)pow(2.,(double)(lut_size))); } else { assert (TRUE == sram_ports[i]->mode_select); - mode_bit_port = sram_ports[i]; num_mode_sram = sram_ports[i]->size; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index c51e8ebaa..b2531f9b3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -49,7 +49,6 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, int num_segment, t_segment_inf* segments, t_syn_verilog_opts fpga_verilog_opts) { int itrack, iseg, cost_index; - char* chan_prefix = NULL; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; FILE* fp = NULL; @@ -681,7 +680,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "wire [0:%d] %s_size%d_%d_inbus;\n", mux_size - 1, verilog_model->prefix, mux_size, verilog_model->cnt); - char* name_mux = (char *) my_malloc(sizeof(char)*(strlen(verilog_model->prefix) + 5 + char* name_mux = (char *) my_malloc(sizeof(char)*(1 + + strlen(verilog_model->prefix) + 5 + strlen(my_itoa(mux_size)) + 1 + strlen(my_itoa(verilog_model->cnt)) + 5)); sprintf(name_mux, "/%s_size%d_%d_/in", verilog_model->prefix, mux_size, verilog_model->cnt); @@ -1461,7 +1461,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model = switch_inf[switch_index].spice_model; - char* name_mux = (char *) my_malloc(sizeof(char)*(strlen(verilog_model->prefix) + 5 + char* name_mux = (char *) my_malloc(sizeof(char)*(1 + strlen(verilog_model->prefix) + 5 + strlen(my_itoa(mux_size)) + 1 + strlen(my_itoa(verilog_model->cnt)) + 5)); sprintf(name_mux, "/%s_size%d_%d_/in", verilog_model->prefix, mux_size, verilog_model->cnt); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index 84c857ebe..ada7a8767 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -252,8 +252,7 @@ void verilog_generate_sdc_clock_period(t_sdc_opts sdc_opts, fprintf(fp, "create_clock "); if (NULL != strstr(clock_port[iport]->prefix,"prog")) { fprintf(fp, "%s -period 100 -waveform {0 50}\n", - clock_port[iport]->prefix, - critical_path_delay, critical_path_delay/2); + clock_port[iport]->prefix); } else { fprintf(fp, "%s -period %.4g -waveform {0 %.4g}\n", @@ -1467,12 +1466,11 @@ void verilog_generate_sdc_disable_unused_grids_muxs(FILE* fp, t_grid_tile** LL_grid, t_block* LL_block) { - int ix, iy, iblk, itype, i_num_rr_nodes, i_fan_in; + int ix, iy, iblk, itype; int blk_id; t_type_ptr type; t_phy_pb* cur_phy_pb; t_rr_graph* cur_rr_graph; - t_rr_node* cur_rr_node; char* grid_instance_name=NULL; char* grid_sub_instance_name=NULL; char* grid_prefix=NULL; @@ -1539,7 +1537,7 @@ void dump_sdc_rec_one_pb_muxes(FILE* fp, t_pb_graph_node* cur_pb_graph_node) { int mode_index; - int ipb, jpb, child_mode_index; + int ipb, jpb; t_pb_type* cur_pb_type = NULL; cur_pb_type = cur_pb_graph_node->pb_type; @@ -1592,8 +1590,6 @@ void dump_sdc_pb_graph_pin_muxes (FILE* fp, t_pb_graph_pin pb_graph_pin) { int i_fan_in, datapath_id, fan_in; int level_changing = 0; - int mode_index; - int num_mux_input; t_spice_model* mux_spice_model; t_rr_node cur_node = rr_graph->rr_node[pb_graph_pin.rr_node_index_physical_pb]; t_pb_type* cur_pb_type = pb_graph_pin.parent_node->pb_type; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c index 8864b6f6e..bde8a7211 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c @@ -57,7 +57,6 @@ void sdc_dump_annotation(char* from_path, // includes the cell float min_value = 0; float max_value = 0; - int i,j; // Find in the annotations the min and max if (0 != cur_edge->delay_min) { @@ -82,22 +81,18 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode, char* instance_name) { - int iedge, ipin; + int iedge; int fan_in = 0; t_interconnect* cur_interc = NULL; enum e_interconnect verilog_interc_type = DIRECT_INTERC; t_pb_graph_pin* src_pb_graph_pin = NULL; t_pb_graph_node* src_pb_graph_node = NULL; - t_pb_type* src_pb_type = NULL; t_pb_graph_node* des_pb_graph_node = NULL; - char* from_path_int = NULL; - char* to_path_int = NULL; char* from_path = NULL; char* to_path = NULL; - boolean interc_is_disabled = FALSE; char* set_disable_path; t_pb_graph_pin* cur_pin_disable; @@ -156,7 +151,6 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Source pin, node, pb_type*/ src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; src_pb_graph_node = src_pb_graph_pin->parent_node; - src_pb_type = src_pb_graph_node->pb_type; /* Des pin, node, pb_type */ des_pb_graph_node = des_pb_graph_pin->parent_node; @@ -183,7 +177,6 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, /* 2. spice_model is a wire */ assert (NULL != cur_interc->spice_model); assert (SPICE_MODEL_MUX == cur_interc->spice_model->type); - ipin = 0; for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { continue; @@ -193,7 +186,6 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Source pin, node, pb_type*/ src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; src_pb_graph_node = src_pb_graph_pin->parent_node; - src_pb_type = src_pb_graph_node->pb_type; /* Des pin, node, pb_type */ des_pb_graph_node = des_pb_graph_pin->parent_node; // Generation of the paths for the dumping of the annotations @@ -427,7 +419,7 @@ void sdc_rec_dump_child_pb_graph_node(t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_node* cur_pb_graph_node, char* instance_name) { - int mode_index, ipb, jpb, child_mode_index; + int mode_index, ipb, jpb; t_pb_type* cur_pb_type = NULL; /* Check the file handler */ @@ -460,7 +452,7 @@ void sdc_rec_dump_child_pb_graph_node(t_sram_orgz_info* cur_sram_orgz_info, sdc_dump_cur_node_constraints(cur_sram_orgz_info, fp, cur_pb_graph_node, mode_index, instance_name); // graph_head only has one pb_type } -return; + return; } void sdc_dump_all_pb_graph_nodes(FILE* fp, @@ -479,7 +471,7 @@ void dump_sdc_physical_blocks(t_sram_orgz_info* cur_sram_orgz_info, int type_descriptor_mode, char* instance_name) { - FILE* fp; + FILE* fp; /* Check if the path exists*/ fp = fopen (sdc_path,"w"); @@ -496,7 +488,7 @@ void dump_sdc_physical_blocks(t_sram_orgz_info* cur_sram_orgz_info, sdc_dump_all_pb_graph_nodes(fp, cur_sram_orgz_info, type_descriptor_mode, instance_name); -/* close file */ + /* close file */ fclose(fp); return; @@ -518,6 +510,7 @@ void verilog_generate_sdc_constrain_pb_types(t_sram_orgz_info* cur_sram_orgz_inf dump_sdc_physical_blocks(cur_sram_orgz_info, sdc_path, itype, instance_name); } } -return; + + return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 5db4558c6..fb2e89133 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -87,7 +87,7 @@ void dump_verilog_submodule_timing(FILE* fp, void dump_verilog_submodule_signal_init(FILE* fp, t_spice_model* cur_spice_model) { - int iport, ipin; + int iport; int num_input_port; t_spice_model_port** input_port= NULL; input_port = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); @@ -1796,7 +1796,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, int num_sram_port, t_spice_model_port** sram_port) { - int i, j, level, nextlevel, sram_idx; + int i, j, level, nextlevel; int out_idx; int mux_basis_cnt = 0; int special_basis_cnt = 0; @@ -1816,7 +1816,6 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, for (i = 0; i < spice_mux_arch.num_level; i++) { level = spice_mux_arch.num_level - i; nextlevel = spice_mux_arch.num_level - i - 1; - sram_idx = nextlevel * spice_mux_arch.num_input_basis; /* Check */ assert(nextlevel > -1); fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", @@ -2561,7 +2560,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, t_spice_model_port** input_port = NULL; t_spice_model_port** output_port = NULL; t_spice_model_port** sram_port = NULL; - int iport, ipin, iedge; + int iport, ipin; int sram_port_index = OPEN; int mode_port_index = OPEN; int mode_lsb = 0; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index c6abe57c9..dbfb5fafb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -3237,7 +3237,7 @@ char* gen_verilog_one_routing_channel_instance_name(t_rr_type chan_type, ret = (char*)my_malloc(strlen(convert_chan_type_to_string(chan_type)) + 1 + strlen(my_itoa(x)) + 2 + strlen(my_itoa(y)) - + 1 + 1); + + 4 + 1); sprintf(ret, "%s_%d__%d__0_", convert_chan_type_to_string(chan_type), @@ -3366,8 +3366,7 @@ char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy(t_pb_graph_pin* cur_pb /* Go to upper level */ temp = temp->parent_pb_graph_node; my_free(cur_name); - } - + } return full_name; } diff --git a/vpr7_x2p/vpr/SRC/main.c b/vpr7_x2p/vpr/SRC/main.c index 41165e2ea..0f3ac9599 100644 --- a/vpr7_x2p/vpr/SRC/main.c +++ b/vpr7_x2p/vpr/SRC/main.c @@ -73,6 +73,11 @@ int main(int argc, char **argv) { /* free data structures */ vpr_free_all(Arch, Options, vpr_setup); + + /* Close those file handlers for a clean valgrind */ + fclose(stdin); + fclose(stdout); + fclose(stderr); /* Return 0 to single success to scripts */ return 0; diff --git a/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c b/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c index f0b74dc5f..6fc05be31 100644 --- a/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c +++ b/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c @@ -40,8 +40,6 @@ static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_pl static void copy_delay( float* base, float* source, t_linked_int* index ); static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition ); static float* copy_from_float_array( float* source, int num ); -static t_buffer_plan add_delay_to_buffer_plan( t_buffer_plan plan, float Tdel ); - void try_buffer_for_net( int inet, t_rc_node** rc_node_free_list, t_linked_rc_edge** rc_edge_free_list, t_linked_rc_ptr* rr_node_to_rc_node, float* net_delay ); /* memristor */ @@ -328,27 +326,6 @@ static t_buffer_plan_list try_buffer_rc_tree (t_rc_node *rc_node, int num_pins, return result; } -static void add_delay_to_buffer_list( t_buffer_plan_list list, float Tdel , boolean skip_first ) -{ - t_buffer_plan_node* traverse = list.front; - if ( skip_first && traverse != NULL ) - { - traverse = traverse->next; - } - while ( traverse != NULL ) - { - traverse->value = add_delay_to_buffer_plan( traverse->value, Tdel ); - traverse = traverse->next; - } -} - -static t_buffer_plan add_delay_to_buffer_plan( t_buffer_plan plan, float Tdel ) -{ - add_delay_to_array( plan.sink_delay, plan.sink_head, Tdel ); - plan.Tdel += Tdel; - return plan; -} - static t_buffer_plan_list get_empty_buffer_plan_list( ) { t_buffer_plan_list list; diff --git a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c index 470a46d5f..74a3f6709 100644 --- a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c +++ b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c @@ -16,7 +16,6 @@ t_linked_int* insert_in_int_list2 (t_linked_int *head, int data ) t_linked_int* copy_from_list( t_linked_int* base, t_linked_int* target ) { - t_linked_int* traverse = target; while ( target != NULL ) { base = insert_in_int_list2( base, target->data ); diff --git a/vpr7_x2p/vpr/SRC/pack/cluster_legality.c b/vpr7_x2p/vpr/SRC/pack/cluster_legality.c index fb91fa2f5..df85e0c10 100755 --- a/vpr7_x2p/vpr/SRC/pack/cluster_legality.c +++ b/vpr7_x2p/vpr/SRC/pack/cluster_legality.c @@ -1252,14 +1252,13 @@ void force_post_place_route_cb_input_pins(int iblock) { int i, j, k, ipin, net_index, ext_net; int pin_offset; boolean has_ext_source, success; - int curr_ext_output, curr_ext_input, curr_ext_clock; + int curr_ext_input, curr_ext_clock; t_pb_graph_node *pb_graph_node; pb_graph_node = block[iblock].pb->pb_graph_node; pin_offset = block[iblock].z * (pb_graph_node->pb_type->num_input_pins + pb_graph_node->pb_type->num_output_pins + pb_graph_node->pb_type->num_clock_pins); curr_ext_input = ext_input_rr_node_index; - curr_ext_output = ext_output_rr_node_index; curr_ext_clock = ext_clock_rr_node_index; for (i = 0; i < num_nets_in_cluster; i++) { diff --git a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c index 55e130c5c..40838f6b8 100755 --- a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c +++ b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c @@ -1780,8 +1780,6 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, t_token * tokens; int num_tokens; int i_tokens, cur_port_index, cur_pin_index; - int i_index_mode; - t_mode* cur_mode; t_pb_graph_node** cur_node; int index_cur_node, i_index_cur_node; t_pb_graph_node* tmp_node; diff --git a/vpr7_x2p/vpr/SRC/place/place.c b/vpr7_x2p/vpr/SRC/place/place.c index 95cab13f3..c3f97863e 100755 --- a/vpr7_x2p/vpr/SRC/place/place.c +++ b/vpr7_x2p/vpr/SRC/place/place.c @@ -1203,8 +1203,8 @@ static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) { * Returns abort_swap. */ int imacro, imember; - int x_swap_offset, y_swap_offset, z_swap_offset, x_from, y_from, z_from, b_to; - int curr_b_from, curr_x_from, curr_y_from, curr_z_from, curr_b_to, curr_x_to, curr_y_to, curr_z_to; + int x_swap_offset, y_swap_offset, z_swap_offset, x_from, y_from, z_from; + int curr_b_from, curr_x_from, curr_y_from, curr_z_from, curr_x_to, curr_y_to, curr_z_to; int abort_swap = FALSE; /* int to_imacro;*/ /* Xifan TANG: for more checking */ @@ -1213,8 +1213,6 @@ static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) { y_from = block[b_from].y; z_from = block[b_from].z; - b_to = grid[x_to][y_to].blocks[z_to]; - get_imacro_from_iblk(&imacro, b_from, pl_macros, num_pl_macros); if ( imacro != -1) { // b_from is part of a macro, I need to swap the whole macro @@ -1291,7 +1289,6 @@ static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) { curr_y_to = curr_y_from + y_swap_offset; curr_z_to = curr_z_from + z_swap_offset; */ - curr_b_to = grid[curr_x_to][curr_y_to].blocks[curr_z_to]; abort_swap = setup_blocks_affected(curr_b_from, curr_x_to, curr_y_to, curr_z_to); } // Finish going through all the blocks in the macro } @@ -1320,7 +1317,7 @@ static enum swap_result try_swap(float t, float *cost, float *bb_cost, float *ti * rlim is the range limiter. */ enum swap_result keep_switch; - int b_from, x_from, y_from, z_from, x_to, y_to, z_to, b_to; + int b_from, x_from, y_from, z_from, x_to, y_to, z_to; int num_nets_affected; float delta_c, bb_delta_c, timing_delta_c, delay_delta_c; int inet, iblk, bnum, iblk_pin, inet_affected; diff --git a/vpr7_x2p/vpr/SRC/place/place_macro.c b/vpr7_x2p/vpr/SRC/place/place_macro.c index daa1ea137..e9463e8ae 100644 --- a/vpr7_x2p/vpr/SRC/place/place_macro.c +++ b/vpr7_x2p/vpr/SRC/place/place_macro.c @@ -192,7 +192,7 @@ static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_nu int iblk, from_iblk_pin, to_iblk_pin, from_inet, to_inet, from_idirect, to_idirect, from_src_or_sink, to_src_or_sink; - int next_iblk, curr_iblk, next_inet, curr_inet; + int next_iblk, next_inet, curr_inet; int num_blk_pins, num_macro; int imember; @@ -236,7 +236,6 @@ static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_nu // Start finding the other members while (next_inet != OPEN) { - curr_iblk = next_iblk; curr_inet = next_inet; // Assume that carry chains only has 1 sink - direct connection diff --git a/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.c b/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.c index cdd6c9d50..b82961704 100644 --- a/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.c +++ b/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.c @@ -79,7 +79,7 @@ int alloc_and_add_fully_capacity_rr_edges_to_source_opin(t_type_ptr cur_type_des t_rr_node** source_rr_node, t_rr_node** opin_rr_node) { int ret = 0; - int isrc, iopin, offset, iedge; + int isrc, iopin, offset; for (isrc = 0; isrc < num_source_rr_node; isrc++) { source_rr_node[isrc]->capacity = 1; diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c b/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c index 80169617d..c33b8a4a6 100644 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c +++ b/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c @@ -470,7 +470,6 @@ int add_opin_list_ipin_list_fast_edge(int num_opins, t_rr_node** opin_list, int ipin, iedge, to_node, jpin; int num_ipin_sink = 0; t_linked_int* ipin_sink_head = NULL; - t_linked_int* ipin_sink_list_node; int* ipin_sink_index = (int*)my_malloc(sizeof(int)*num_ipins); int add_edge_counter = 0; diff --git a/vpr7_x2p/vpr/SRC/util/vpr_utils.c b/vpr7_x2p/vpr/SRC/util/vpr_utils.c index 99fd4b92f..a7c1dbf3a 100755 --- a/vpr7_x2p/vpr/SRC/util/vpr_utils.c +++ b/vpr7_x2p/vpr/SRC/util/vpr_utils.c @@ -396,10 +396,8 @@ t_pb_graph_pin* get_pb_graph_node_pin_from_vpack_net(int inet, int ipin) { t_pb_graph_pin* get_pb_graph_node_pin_from_clb_net(int inet, int ipin) { int iblock, target_pin; - t_pb_graph_node *pb_graph_node; iblock = clb_net[inet].node_block[ipin]; - pb_graph_node = block[iblock].pb->pb_graph_node; target_pin = clb_net[inet].node_block_pin[ipin];